wil6210: TX vring optimization
Tx vring needs to be enlarged to get better performance for traffic over 2Gbps. Signed-off-by: Hamad Kadmany <qca_hkadmany@qca.qualcomm.com> Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2015 Qualcomm Atheros, Inc.
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* Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -68,13 +68,13 @@ static void wil_print_vring(struct seq_file *s, struct wil6210_priv *wil,
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seq_puts(s, "???\n");
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}
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if (vring->va && (vring->size < 1025)) {
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if (vring->va && (vring->size <= (1 << WIL_RING_SIZE_ORDER_MAX))) {
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uint i;
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for (i = 0; i < vring->size; i++) {
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volatile struct vring_tx_desc *d = &vring->va[i].tx;
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if ((i % 64) == 0 && (i != 0))
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if ((i % 128) == 0 && (i != 0))
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seq_puts(s, "\n");
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seq_printf(s, "%c", (d->dma.status & BIT(0)) ?
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_s : (vring->ctx[i].skb ? _h : 'h'));
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@ -51,7 +51,7 @@ static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
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#define WIL_TX_Q_LEN_DEFAULT (4000)
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#define WIL_RX_RING_SIZE_ORDER_DEFAULT (10)
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#define WIL_TX_RING_SIZE_ORDER_DEFAULT (10)
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#define WIL_TX_RING_SIZE_ORDER_DEFAULT (12)
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#define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7)
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#define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */
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/* limit ring size in range [32..32k] */
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