Merge branch 'phy-aquantia-improvements'
Heiner Kallweit says: ==================== net: phy: aquantia: number of improvements This patch series is based on work from Andrew. I adjusted and added certain parts. The series improves few aspects of driver, no functional change intended. v2: - add my SoB to patch 1 - leave kernel.h in in patch 2 ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
ee825e8bc7
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@ -10,10 +10,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/mdio.h>
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#define PHY_ID_AQ1202 0x03a1b445
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#define PHY_ID_AQ2104 0x03a1b460
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@ -22,7 +19,49 @@
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#define PHY_ID_AQR107 0x03a1b4e0
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#define PHY_ID_AQR405 0x03a1b4b0
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static int aquantia_config_aneg(struct phy_device *phydev)
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#define MDIO_AN_TX_VEND_STATUS1 0xc800
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#define MDIO_AN_TX_VEND_STATUS1_10BASET (0x0 << 1)
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#define MDIO_AN_TX_VEND_STATUS1_100BASETX (0x1 << 1)
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#define MDIO_AN_TX_VEND_STATUS1_1000BASET (0x2 << 1)
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#define MDIO_AN_TX_VEND_STATUS1_10GBASET (0x3 << 1)
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#define MDIO_AN_TX_VEND_STATUS1_2500BASET (0x4 << 1)
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#define MDIO_AN_TX_VEND_STATUS1_5000BASET (0x5 << 1)
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#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK (0x7 << 1)
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#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
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#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
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#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
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#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
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/* Vendor specific 1, MDIO_MMD_VEND1 */
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#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
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#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
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#define VEND1_GLOBAL_INT_STD_MASK 0xff00
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#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
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#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
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#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
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#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
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#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
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#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
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#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
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#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
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#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
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#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
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#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
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#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
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#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
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#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
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static int aqr_config_aneg(struct phy_device *phydev)
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{
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linkmode_copy(phydev->supported, phy_10gbit_features);
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linkmode_copy(phydev->advertising, phydev->supported);
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@ -30,44 +69,55 @@ static int aquantia_config_aneg(struct phy_device *phydev)
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return 0;
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}
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static int aquantia_config_intr(struct phy_device *phydev)
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static int aqr_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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err = phy_write_mmd(phydev, MDIO_MMD_AN, 0xd401, 1);
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err = phy_write_mmd(phydev, MDIO_MMD_AN,
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MDIO_AN_TX_VEND_INT_MASK2,
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MDIO_AN_TX_VEND_INT_MASK2_LINK);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff00, 1);
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_INT_STD_MASK,
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VEND1_GLOBAL_INT_STD_MASK_ALL);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff01, 0x1001);
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_INT_VEND_MASK,
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VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
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VEND1_GLOBAL_INT_VEND_MASK_AN);
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} else {
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err = phy_write_mmd(phydev, MDIO_MMD_AN, 0xd401, 0);
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err = phy_write_mmd(phydev, MDIO_MMD_AN,
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MDIO_AN_TX_VEND_INT_MASK2, 0);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff00, 0);
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_INT_STD_MASK, 0);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff01, 0);
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_INT_VEND_MASK, 0);
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}
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return err;
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}
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static int aquantia_ack_interrupt(struct phy_device *phydev)
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static int aqr_ack_interrupt(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xcc01);
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reg = phy_read_mmd(phydev, MDIO_MMD_AN,
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MDIO_AN_TX_VEND_INT_STATUS2);
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return (reg < 0) ? reg : 0;
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}
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static int aquantia_read_status(struct phy_device *phydev)
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static int aqr_read_status(struct phy_device *phydev)
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{
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int reg;
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@ -78,21 +128,20 @@ static int aquantia_read_status(struct phy_device *phydev)
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else
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phydev->link = 0;
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xc800);
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
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mdelay(10);
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xc800);
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
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switch (reg) {
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case 0x9:
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switch (reg & MDIO_AN_TX_VEND_STATUS1_RATE_MASK) {
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case MDIO_AN_TX_VEND_STATUS1_2500BASET:
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phydev->speed = SPEED_2500;
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break;
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case 0x5:
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case MDIO_AN_TX_VEND_STATUS1_1000BASET:
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phydev->speed = SPEED_1000;
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break;
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case 0x3:
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case MDIO_AN_TX_VEND_STATUS1_100BASETX:
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phydev->speed = SPEED_100;
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break;
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case 0x7:
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default:
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phydev->speed = SPEED_10000;
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break;
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@ -102,88 +151,82 @@ static int aquantia_read_status(struct phy_device *phydev)
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return 0;
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}
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static struct phy_driver aquantia_driver[] = {
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static struct phy_driver aqr_driver[] = {
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{
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.phy_id = PHY_ID_AQ1202,
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.phy_id_mask = 0xfffffff0,
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PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
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.name = "Aquantia AQ1202",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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.phy_id = PHY_ID_AQ2104,
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.phy_id_mask = 0xfffffff0,
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PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
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.name = "Aquantia AQ2104",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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.phy_id = PHY_ID_AQR105,
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.phy_id_mask = 0xfffffff0,
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PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
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.name = "Aquantia AQR105",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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.phy_id = PHY_ID_AQR106,
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.phy_id_mask = 0xfffffff0,
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PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
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.name = "Aquantia AQR106",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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.phy_id = PHY_ID_AQR107,
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.phy_id_mask = 0xfffffff0,
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PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
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.name = "Aquantia AQR107",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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.phy_id = PHY_ID_AQR405,
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.phy_id_mask = 0xfffffff0,
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PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
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.name = "Aquantia AQR405",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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};
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module_phy_driver(aquantia_driver);
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module_phy_driver(aqr_driver);
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static struct mdio_device_id __maybe_unused aquantia_tbl[] = {
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{ PHY_ID_AQ1202, 0xfffffff0 },
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{ PHY_ID_AQ2104, 0xfffffff0 },
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{ PHY_ID_AQR105, 0xfffffff0 },
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{ PHY_ID_AQR106, 0xfffffff0 },
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{ PHY_ID_AQR107, 0xfffffff0 },
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{ PHY_ID_AQR405, 0xfffffff0 },
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static struct mdio_device_id __maybe_unused aqr_tbl[] = {
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, aquantia_tbl);
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MODULE_DEVICE_TABLE(mdio, aqr_tbl);
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MODULE_DESCRIPTION("Aquantia PHY driver");
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MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
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