arm/arm64: smccc: Implement SMCCC v1.1 inline primitive
One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that would otherwise be clobbered by SMCCC v1.0. Reviewed-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Marc Zyngier
Catalin Marinas
parent
ded4c39e93
commit
f2d3b2e875
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@ -150,5 +150,146 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
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#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__)
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/* SMCCC v1.1 implementation madness follows */
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#ifdef CONFIG_ARM64
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#define SMCCC_SMC_INST "smc #0"
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#define SMCCC_HVC_INST "hvc #0"
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#elif defined(CONFIG_ARM)
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#include <asm/opcodes-sec.h>
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#include <asm/opcodes-virt.h>
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#define SMCCC_SMC_INST __SMC(0)
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#define SMCCC_HVC_INST __HVC(0)
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#endif
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#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x
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#define __count_args(...) \
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___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0)
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#define __constraint_write_0 \
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"+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3)
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#define __constraint_write_1 \
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"+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3)
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#define __constraint_write_2 \
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"+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3)
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#define __constraint_write_3 \
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"+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3)
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#define __constraint_write_4 __constraint_write_3
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#define __constraint_write_5 __constraint_write_4
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#define __constraint_write_6 __constraint_write_5
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#define __constraint_write_7 __constraint_write_6
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#define __constraint_read_0
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#define __constraint_read_1
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#define __constraint_read_2
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#define __constraint_read_3
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#define __constraint_read_4 "r" (r4)
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#define __constraint_read_5 __constraint_read_4, "r" (r5)
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#define __constraint_read_6 __constraint_read_5, "r" (r6)
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#define __constraint_read_7 __constraint_read_6, "r" (r7)
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#define __declare_arg_0(a0, res) \
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struct arm_smccc_res *___res = res; \
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register u32 r0 asm("r0") = a0; \
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register unsigned long r1 asm("r1"); \
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register unsigned long r2 asm("r2"); \
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register unsigned long r3 asm("r3")
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#define __declare_arg_1(a0, a1, res) \
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struct arm_smccc_res *___res = res; \
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register u32 r0 asm("r0") = a0; \
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register typeof(a1) r1 asm("r1") = a1; \
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register unsigned long r2 asm("r2"); \
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register unsigned long r3 asm("r3")
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#define __declare_arg_2(a0, a1, a2, res) \
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struct arm_smccc_res *___res = res; \
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register u32 r0 asm("r0") = a0; \
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register typeof(a1) r1 asm("r1") = a1; \
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register typeof(a2) r2 asm("r2") = a2; \
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register unsigned long r3 asm("r3")
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#define __declare_arg_3(a0, a1, a2, a3, res) \
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struct arm_smccc_res *___res = res; \
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register u32 r0 asm("r0") = a0; \
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register typeof(a1) r1 asm("r1") = a1; \
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register typeof(a2) r2 asm("r2") = a2; \
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register typeof(a3) r3 asm("r3") = a3
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#define __declare_arg_4(a0, a1, a2, a3, a4, res) \
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__declare_arg_3(a0, a1, a2, a3, res); \
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register typeof(a4) r4 asm("r4") = a4
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#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \
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__declare_arg_4(a0, a1, a2, a3, a4, res); \
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register typeof(a5) r5 asm("r5") = a5
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#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \
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__declare_arg_5(a0, a1, a2, a3, a4, a5, res); \
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register typeof(a6) r6 asm("r6") = a6
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#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \
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__declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \
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register typeof(a7) r7 asm("r7") = a7
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#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__)
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#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__)
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#define ___constraints(count) \
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: __constraint_write_ ## count \
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: __constraint_read_ ## count \
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: "memory"
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#define __constraints(count) ___constraints(count)
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/*
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* We have an output list that is not necessarily used, and GCC feels
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* entitled to optimise the whole sequence away. "volatile" is what
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* makes it stick.
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*/
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#define __arm_smccc_1_1(inst, ...) \
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do { \
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__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \
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asm volatile(inst "\n" \
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__constraints(__count_args(__VA_ARGS__))); \
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if (___res) \
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*___res = (typeof(*___res)){r0, r1, r2, r3}; \
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} while (0)
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/*
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* arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call
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*
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* This is a variadic macro taking one to eight source arguments, and
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* an optional return structure.
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*
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* @a0-a7: arguments passed in registers 0 to 7
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* @res: result values from registers 0 to 3
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*
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* This macro is used to make SMC calls following SMC Calling Convention v1.1.
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* The content of the supplied param are copied to registers 0 to 7 prior
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* to the SMC instruction. The return values are updated with the content
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* from register 0 to 3 on return from the SMC instruction if not NULL.
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*/
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#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__)
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/*
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* arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call
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*
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* This is a variadic macro taking one to eight source arguments, and
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* an optional return structure.
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*
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* @a0-a7: arguments passed in registers 0 to 7
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* @res: result values from registers 0 to 3
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*
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* This macro is used to make HVC calls following SMC Calling Convention v1.1.
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* The content of the supplied param are copied to registers 0 to 7 prior
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* to the HVC instruction. The return values are updated with the content
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* from register 0 to 3 on return from the HVC instruction if not NULL.
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*/
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#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__)
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#endif /*__ASSEMBLY__*/
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#endif /*__LINUX_ARM_SMCCC_H*/
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