wcn36xx: Add support for 3680
3680 has a few registers on other addresses. Signed-off-by: Pontus Fuchs <pontus.fuchs@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -44,6 +44,14 @@ static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data)
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writel(data, wcn->mmio + addr);
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}
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#define wcn36xx_dxe_write_register_x(wcn, reg, reg_data) \
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do { \
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if (wcn->chip_version == WCN36XX_CHIP_3680) \
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wcn36xx_dxe_write_register(wcn, reg ## _3680, reg_data); \
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else \
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wcn36xx_dxe_write_register(wcn, reg ## _3660, reg_data); \
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} while (0) \
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static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data)
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{
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*data = readl(wcn->mmio + addr);
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@ -680,7 +688,7 @@ int wcn36xx_dxe_init(struct wcn36xx *wcn)
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/* Setting interrupt path */
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reg_data = WCN36XX_DXE_CCU_INT;
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wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CCU_INT, reg_data);
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wcn36xx_dxe_write_register_x(wcn, WCN36XX_DXE_REG_CCU_INT, reg_data);
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/***************************************/
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/* Init descriptors for TX LOW channel */
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@ -28,11 +28,11 @@ H2H_TEST_RX_TX = DMA2
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*/
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/* DXE registers */
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#define WCN36XX_DXE_MEM_BASE 0x03000000
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#define WCN36XX_DXE_MEM_REG 0x202000
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#define WCN36XX_DXE_CCU_INT 0xA0011
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#define WCN36XX_DXE_REG_CCU_INT 0x200b10
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#define WCN36XX_DXE_REG_CCU_INT_3660 0x200b10
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#define WCN36XX_DXE_REG_CCU_INT_3680 0x2050dc
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/* TODO This must calculated properly but not hardcoded */
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#define WCN36XX_DXE_CTRL_TX_L 0x328a44
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@ -221,6 +221,17 @@ static void wcn36xx_feat_caps_info(struct wcn36xx *wcn)
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}
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}
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static void wcn36xx_detect_chip_version(struct wcn36xx *wcn)
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{
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if (get_feat_caps(wcn->fw_feat_caps, DOT11AC)) {
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wcn36xx_info("Chip is 3680\n");
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wcn->chip_version = WCN36XX_CHIP_3680;
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} else {
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wcn36xx_info("Chip is 3660\n");
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wcn->chip_version = WCN36XX_CHIP_3660;
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}
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}
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static int wcn36xx_start(struct ieee80211_hw *hw)
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{
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struct wcn36xx *wcn = hw->priv;
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@ -267,6 +278,16 @@ static int wcn36xx_start(struct ieee80211_hw *hw)
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goto out_free_smd_buf;
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}
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if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24)) {
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ret = wcn36xx_smd_feature_caps_exchange(wcn);
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if (ret)
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wcn36xx_warn("Exchange feature caps failed\n");
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else
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wcn36xx_feat_caps_info(wcn);
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}
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wcn36xx_detect_chip_version(wcn);
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/* DMA channel initialization */
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ret = wcn36xx_dxe_init(wcn);
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if (ret) {
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@ -276,13 +297,6 @@ static int wcn36xx_start(struct ieee80211_hw *hw)
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wcn36xx_debugfs_init(wcn);
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if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24)) {
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ret = wcn36xx_smd_feature_caps_exchange(wcn);
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if (ret)
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wcn36xx_warn("Exchange feature caps failed\n");
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else
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wcn36xx_feat_caps_info(wcn);
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}
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INIT_LIST_HEAD(&wcn->vif_list);
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return 0;
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@ -178,6 +178,7 @@ struct wcn36xx {
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u8 fw_minor;
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u8 fw_major;
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u32 fw_feat_caps[WCN36XX_HAL_CAPS_SIZE];
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u32 chip_version;
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/* extra byte for the NULL termination */
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u8 crm_version[WCN36XX_HAL_VERSION_LENGTH + 1];
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@ -225,6 +226,9 @@ struct wcn36xx {
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};
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#define WCN36XX_CHIP_3660 0
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#define WCN36XX_CHIP_3680 1
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static inline bool wcn36xx_is_fw_version(struct wcn36xx *wcn,
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u8 major,
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u8 minor,
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