Merge tag 'drm-intel-fixes-2015-04-08' of git://anongit.freedesktop.org/drm-intel into drm-fixes
three commits, all cc: stable, to address Baytrail suspend/resume issues. * tag 'drm-intel-fixes-2015-04-08' of git://anongit.freedesktop.org/drm-intel: drm/i915/vlv: remove wait for previous GFX clk disable request drm/i915/chv: Remove Wait for a previous gfx force-off drm/i915/vlv: save/restore the power context base reg
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commit
f4274e23fb
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@ -1095,6 +1095,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
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/* Gunit-Display CZ domain, 0x182028-0x1821CF */
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/* Gunit-Display CZ domain, 0x182028-0x1821CF */
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s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
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s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
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s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
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s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
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s->pcbr = I915_READ(VLV_PCBR);
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s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
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s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
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/*
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/*
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@ -1189,6 +1190,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
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/* Gunit-Display CZ domain, 0x182028-0x1821CF */
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/* Gunit-Display CZ domain, 0x182028-0x1821CF */
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I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
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I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
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I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
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I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
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I915_WRITE(VLV_PCBR, s->pcbr);
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I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
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I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
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}
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}
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@ -1197,19 +1199,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
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u32 val;
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u32 val;
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int err;
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int err;
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val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
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WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
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#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
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#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
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/* Wait for a previous force-off to settle */
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if (force_on) {
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err = wait_for(!COND, 20);
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if (err) {
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DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
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I915_READ(VLV_GTLC_SURVIVABILITY_REG));
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return err;
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}
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}
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val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
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val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
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val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
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val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
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@ -1094,6 +1094,7 @@ struct vlv_s0ix_state {
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/* Display 2 CZ domain */
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/* Display 2 CZ domain */
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u32 gu_ctl0;
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u32 gu_ctl0;
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u32 gu_ctl1;
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u32 gu_ctl1;
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u32 pcbr;
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u32 clock_gate_dis2;
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u32 clock_gate_dis2;
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};
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};
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