drm/nouveau/kms/nv50: fix handling of gamma since atomic conversion
We've still been directly using the legacy crtc gamma_set() hook even after conversion to atomic modesetting. For userspace clients this was fine, however, fbcon will use the atomic property when it's running on an atomic driver, which means we miss its colormap updates - which is particularly bad for 8bpp framebuffers! This commit converts the driver to use the atomic property + the helper function implementing the legacy hook on top of atomic. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80675 Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs
parent
90df522912
commit
f4778f08a0
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@ -137,8 +137,10 @@ struct nv50_head_atom {
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} mode;
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struct {
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bool visible;
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u32 handle;
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u64 offset:40;
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u8 mode:4;
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} lut;
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struct {
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@ -192,6 +194,7 @@ struct nv50_head_atom {
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union {
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struct {
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bool ilut:1;
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bool core:1;
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bool curs:1;
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};
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@ -200,6 +203,7 @@ struct nv50_head_atom {
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union {
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struct {
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bool ilut:1;
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bool core:1;
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bool curs:1;
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bool view:1;
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@ -661,7 +665,8 @@ nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
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struct nv50_head {
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struct nouveau_crtc base;
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struct {
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struct nouveau_bo *nvbo[1];
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struct nouveau_bo *nvbo[2];
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int next;
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} lut;
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struct nv50_ovly ovly;
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struct nv50_oimm oimm;
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@ -1797,6 +1802,54 @@ nv50_head_lut_clr(struct nv50_head *head)
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}
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}
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static void
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nv50_head_lut_load(struct drm_property_blob *blob, int mode,
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struct nouveau_bo *nvbo)
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{
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struct drm_color_lut *in = (struct drm_color_lut *)blob->data;
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void __iomem *lut = (u8 *)nvbo_kmap_obj_iovirtual(nvbo);
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const int size = blob->length / sizeof(*in);
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int bits, shift, i;
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u16 zero, r, g, b;
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/* This can't happen.. But it shuts the compiler up. */
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if (WARN_ON(size != 256))
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return;
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switch (mode) {
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case 0: /* LORES. */
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case 1: /* HIRES. */
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bits = 11;
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shift = 3;
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zero = 0x0000;
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break;
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case 7: /* INTERPOLATE_257_UNITY_RANGE. */
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bits = 14;
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shift = 0;
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zero = 0x6000;
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break;
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default:
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WARN_ON(1);
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return;
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}
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for (i = 0; i < size; i++) {
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r = (drm_color_lut_extract(in[i]. red, bits) + zero) << shift;
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g = (drm_color_lut_extract(in[i].green, bits) + zero) << shift;
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b = (drm_color_lut_extract(in[i]. blue, bits) + zero) << shift;
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writew(r, lut + (i * 0x08) + 0);
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writew(g, lut + (i * 0x08) + 2);
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writew(b, lut + (i * 0x08) + 4);
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}
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/* INTERPOLATE modes require a "next" entry to interpolate with,
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* so we replicate the last entry to deal with this for now.
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*/
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writew(r, lut + (i * 0x08) + 0);
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writew(g, lut + (i * 0x08) + 2);
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writew(b, lut + (i * 0x08) + 4);
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}
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static void
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nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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@ -1805,20 +1858,18 @@ nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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if ((push = evo_wait(core, 7))) {
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if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
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evo_data(push, asyh->base.depth == 8 ?
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0x80000000 : 0xc0000000);
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evo_data(push, 0x80000000 | asyh->lut.mode << 30);
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evo_data(push, asyh->lut.offset >> 8);
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} else
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if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
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evo_data(push, asyh->base.depth == 8 ?
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0x80000000 : 0xc0000000);
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evo_data(push, 0x80000000 | asyh->lut.mode << 30);
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evo_data(push, asyh->lut.offset >> 8);
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evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
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evo_data(push, asyh->lut.handle);
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} else {
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evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
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evo_data(push, 0x87000000);
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evo_data(push, 0x80000000 | asyh->lut.mode << 24);
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evo_data(push, asyh->lut.offset >> 8);
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evo_data(push, 0x00000000);
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evo_data(push, 0x00000000);
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@ -1901,7 +1952,7 @@ nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
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static void
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nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
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{
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if (asyh->clr.core && (!asyh->set.core || y))
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if (asyh->clr.ilut && (!asyh->set.ilut || y))
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nv50_head_lut_clr(head);
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if (asyh->clr.core && (!asyh->set.core || y))
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nv50_head_core_clr(head);
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@ -1914,7 +1965,15 @@ nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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if (asyh->set.view ) nv50_head_view (head, asyh);
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if (asyh->set.mode ) nv50_head_mode (head, asyh);
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if (asyh->set.core ) nv50_head_lut_set (head, asyh);
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if (asyh->set.ilut ) {
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struct nouveau_bo *nvbo = head->lut.nvbo[head->lut.next];
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struct drm_property_blob *blob = asyh->state.gamma_lut;
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if (blob)
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nv50_head_lut_load(blob, asyh->lut.mode, nvbo);
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asyh->lut.offset = nvbo->bo.offset;
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head->lut.next ^= 1;
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nv50_head_lut_set(head, asyh);
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}
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if (asyh->set.core ) nv50_head_core_set(head, asyh);
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if (asyh->set.curs ) nv50_head_curs_set(head, asyh);
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if (asyh->set.base ) nv50_head_base (head, asyh);
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@ -2048,6 +2107,37 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh,
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asyh->set.view = true;
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}
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static void
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nv50_head_atomic_check_lut(struct nv50_head *head,
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struct nv50_head_atom *armh,
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struct nv50_head_atom *asyh)
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{
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struct nv50_disp *disp = nv50_disp(head->base.base.dev);
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/* An I8 surface without an input LUT makes no sense, and
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* EVO will throw an error if you try.
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*
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* Legacy clients actually cause this due to the order in
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* which they call ioctls, so we will enable the LUT with
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* whatever contents the buffer already contains to avoid
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* triggering the error check.
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*/
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if (!asyh->state.gamma_lut && asyh->base.cpp != 1) {
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asyh->lut.handle = 0;
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asyh->clr.ilut = armh->lut.visible;
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return;
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}
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if (disp->disp->oclass < GF110_DISP) {
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asyh->lut.mode = (asyh->base.cpp == 1) ? 0 : 1;
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asyh->set.ilut = true;
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} else {
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asyh->lut.mode = 7;
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asyh->set.ilut = asyh->state.color_mgmt_changed;
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}
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asyh->lut.handle = disp->mast.base.vram.handle;
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}
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static void
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nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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@ -2133,6 +2223,11 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
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if (asyh->state.mode_changed)
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nv50_head_atomic_check_mode(head, asyh);
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if (asyh->state.color_mgmt_changed ||
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asyh->base.cpp != armh->base.cpp)
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nv50_head_atomic_check_lut(head, armh, asyh);
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asyh->lut.visible = asyh->lut.handle != 0;
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if (asyc) {
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if (asyc->set.scaler)
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nv50_head_atomic_check_view(armh, asyh, asyc);
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@ -2148,7 +2243,8 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
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asyh->core.w = asyh->base.w;
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asyh->core.h = asyh->base.h;
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} else
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if ((asyh->core.visible = asyh->curs.visible)) {
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if ((asyh->core.visible = asyh->curs.visible) ||
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(asyh->core.visible = asyh->lut.visible)) {
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/*XXX: We need to either find some way of having the
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* primary base layer appear black, while still
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* being able to display the other layers, or we
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@ -2166,11 +2262,10 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
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asyh->core.layout = 1;
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asyh->core.block = 0;
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asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
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asyh->lut.handle = disp->mast.base.vram.handle;
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asyh->lut.offset = head->lut.nvbo[0]->bo.offset;
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asyh->set.base = armh->base.cpp != asyh->base.cpp;
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asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
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} else {
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asyh->lut.visible = false;
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asyh->core.visible = false;
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asyh->curs.visible = false;
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asyh->base.cpp = 0;
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@ -2194,8 +2289,10 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
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asyh->clr.curs = true;
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}
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} else {
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asyh->clr.ilut = armh->lut.visible;
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asyh->clr.core = armh->core.visible;
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asyh->clr.curs = armh->curs.visible;
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asyh->set.ilut = asyh->lut.visible;
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asyh->set.core = asyh->core.visible;
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asyh->set.curs = asyh->curs.visible;
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}
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@ -2205,47 +2302,11 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
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return 0;
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}
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static void
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nv50_head_lut_load(struct drm_crtc *crtc)
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{
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struct nv50_disp *disp = nv50_disp(crtc->dev);
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struct nv50_head *head = nv50_head(crtc);
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void __iomem *lut = nvbo_kmap_obj_iovirtual(head->lut.nvbo[0]);
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u16 *r, *g, *b;
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int i;
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r = crtc->gamma_store;
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g = r + crtc->gamma_size;
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b = g + crtc->gamma_size;
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for (i = 0; i < 256; i++) {
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if (disp->disp->oclass < GF110_DISP) {
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writew((*r++ >> 2) + 0x0000, lut + (i * 0x08) + 0);
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writew((*g++ >> 2) + 0x0000, lut + (i * 0x08) + 2);
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writew((*b++ >> 2) + 0x0000, lut + (i * 0x08) + 4);
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} else {
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/* 0x6000 interferes with the 14-bit color??? */
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writew((*r++ >> 2) + 0x6000, lut + (i * 0x08) + 0);
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writew((*g++ >> 2) + 0x6000, lut + (i * 0x08) + 2);
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writew((*b++ >> 2) + 0x6000, lut + (i * 0x08) + 4);
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}
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}
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}
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static const struct drm_crtc_helper_funcs
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nv50_head_help = {
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.atomic_check = nv50_head_atomic_check,
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};
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static int
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nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
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uint32_t size,
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struct drm_modeset_acquire_ctx *ctx)
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{
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nv50_head_lut_load(crtc);
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return 0;
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}
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static void
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nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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@ -2318,7 +2379,7 @@ nv50_head_destroy(struct drm_crtc *crtc)
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static const struct drm_crtc_funcs
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nv50_head_func = {
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.reset = nv50_head_reset,
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.gamma_set = nv50_head_gamma_set,
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.gamma_set = drm_atomic_helper_legacy_gamma_set,
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.destroy = nv50_head_destroy,
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.set_config = drm_atomic_helper_set_config,
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.page_flip = drm_atomic_helper_page_flip,
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@ -4345,7 +4406,6 @@ nv50_display_init(struct drm_device *dev)
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{
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struct drm_encoder *encoder;
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struct drm_plane *plane;
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struct drm_crtc *crtc;
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u32 *push;
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push = evo_wait(nv50_mast(dev), 32);
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@ -4364,10 +4424,6 @@ nv50_display_init(struct drm_device *dev)
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}
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}
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drm_for_each_crtc(crtc, dev) {
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nv50_head_lut_load(crtc);
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}
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drm_for_each_plane(plane, dev) {
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struct nv50_wndw *wndw = nv50_wndw(plane);
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if (plane->funcs != &nv50_wndw)
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