mmc: sdhci-of-esdhc: support both BE and LE host controller
To support little endian eSDHC controller, we redefine both BE and LE IO accessors. In the new accessors, use ioread*/iowrite* instead of in_be32/out_be32 and will select accessors according to endian mode in probe function. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
yangbo lu
Ulf Hansson
parent
e38eeca5c2
commit
f4932cfd22
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@ -24,6 +24,8 @@
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SDHCI_QUIRK_PIO_NEEDS_DELAY | \
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SDHCI_QUIRK_NO_HISPD_BIT)
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#define ESDHC_PROCTL 0x28
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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@ -24,122 +24,318 @@
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#define VENDOR_V_22 0x12
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#define VENDOR_V_23 0x13
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static u32 esdhc_readl(struct sdhci_host *host, int reg)
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struct sdhci_esdhc {
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u8 vendor_ver;
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u8 spec_ver;
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};
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/**
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* esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
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* to make it compatible with SD spec.
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*
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* @host: pointer to sdhci_host
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* @spec_reg: SD spec register address
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* @value: 32bit eSDHC register value on spec_reg address
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*
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* In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
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* registers are 32 bits. There are differences in register size, register
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* address, register function, bit position and function between eSDHC spec
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* and SD spec.
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*
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* Return a fixed up register value
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*/
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static u32 esdhc_readl_fixup(struct sdhci_host *host,
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int spec_reg, u32 value)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_esdhc *esdhc = pltfm_host->priv;
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u32 ret;
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ret = in_be32(host->ioaddr + reg);
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/*
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* The bit of ADMA flag in eSDHC is not compatible with standard
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* SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
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* supported by eSDHC.
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* And for many FSL eSDHC controller, the reset value of field
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* SDHCI_CAN_DO_ADMA1 is one, but some of them can't support ADMA,
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* SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
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* only these vendor version is greater than 2.2/0x12 support ADMA.
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* For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the
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* the verdor version number, oxFE is SDHCI_HOST_VERSION.
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*/
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if ((reg == SDHCI_CAPABILITIES) && (ret & SDHCI_CAN_DO_ADMA1)) {
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u32 tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
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tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
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if (tmp > VENDOR_V_22)
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ret |= SDHCI_CAN_DO_ADMA2;
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if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
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if (esdhc->vendor_ver > VENDOR_V_22) {
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ret = value | SDHCI_CAN_DO_ADMA2;
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return ret;
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}
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}
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ret = value;
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return ret;
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}
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static u16 esdhc_readw(struct sdhci_host *host, int reg)
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static u16 esdhc_readw_fixup(struct sdhci_host *host,
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int spec_reg, u32 value)
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{
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u16 ret;
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int base = reg & ~0x3;
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int shift = (reg & 0x2) * 8;
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int shift = (spec_reg & 0x2) * 8;
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if (unlikely(reg == SDHCI_HOST_VERSION))
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ret = in_be32(host->ioaddr + base) & 0xffff;
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if (spec_reg == SDHCI_HOST_VERSION)
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ret = value & 0xffff;
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else
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ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
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ret = (value >> shift) & 0xffff;
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return ret;
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}
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static u8 esdhc_readb(struct sdhci_host *host, int reg)
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static u8 esdhc_readb_fixup(struct sdhci_host *host,
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int spec_reg, u32 value)
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{
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int base = reg & ~0x3;
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int shift = (reg & 0x3) * 8;
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u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
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u8 ret;
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u8 dma_bits;
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int shift = (spec_reg & 0x3) * 8;
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ret = (value >> shift) & 0xff;
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/*
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* "DMA select" locates at offset 0x28 in SD specification, but on
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* P5020 or P3041, it locates at 0x29.
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*/
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if (reg == SDHCI_HOST_CONTROL) {
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u32 dma_bits;
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dma_bits = in_be32(host->ioaddr + reg);
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if (spec_reg == SDHCI_HOST_CONTROL) {
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/* DMA select is 22,23 bits in Protocol Control Register */
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dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK;
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dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
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/* fixup the result */
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ret &= ~SDHCI_CTRL_DMA_MASK;
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ret |= dma_bits;
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}
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return ret;
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}
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/**
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* esdhc_write*_fixup - Fixup the SD spec register value so that it could be
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* written into eSDHC register.
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*
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* @host: pointer to sdhci_host
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* @spec_reg: SD spec register address
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* @value: 8/16/32bit SD spec register value that would be written
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* @old_value: 32bit eSDHC register value on spec_reg address
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*
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* In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
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* registers are 32 bits. There are differences in register size, register
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* address, register function, bit position and function between eSDHC spec
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* and SD spec.
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*
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* Return a fixed up register value
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*/
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static u32 esdhc_writel_fixup(struct sdhci_host *host,
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int spec_reg, u32 value, u32 old_value)
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{
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u32 ret;
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/*
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* Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
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* when SYSCTL[RSTD] is set for some special operations.
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* No any impact on other operation.
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*/
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if (spec_reg == SDHCI_INT_ENABLE)
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ret = value | SDHCI_INT_BLK_GAP;
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else
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ret = value;
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return ret;
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}
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static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
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static u32 esdhc_writew_fixup(struct sdhci_host *host,
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int spec_reg, u16 value, u32 old_value)
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{
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/*
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* Enable IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
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* when SYSCTL[RSTD]) is set for some special operations.
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* No any impact other operation.
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*/
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if (reg == SDHCI_INT_ENABLE)
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val |= SDHCI_INT_BLK_GAP;
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sdhci_be32bs_writel(host, val, reg);
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}
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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int shift = (spec_reg & 0x2) * 8;
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u32 ret;
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static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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if (reg == SDHCI_BLOCK_SIZE) {
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switch (spec_reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below. Return old value.
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*/
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pltfm_host->xfer_mode_shadow = value;
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return old_value;
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case SDHCI_COMMAND:
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ret = (value << 16) | pltfm_host->xfer_mode_shadow;
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return ret;
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}
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ret = old_value & (~(0xffff << shift));
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ret |= (value << shift);
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if (spec_reg == SDHCI_BLOCK_SIZE) {
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/*
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* Two last DMA bits are reserved, and first one is used for
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* non-standard blksz of 4096 bytes that we don't support
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* yet. So clear the DMA boundary bits.
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*/
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
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}
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sdhci_be32bs_writew(host, val, reg);
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return ret;
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}
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static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
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static u32 esdhc_writeb_fixup(struct sdhci_host *host,
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int spec_reg, u8 value, u32 old_value)
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{
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u32 ret;
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u32 dma_bits;
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u8 tmp;
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int shift = (spec_reg & 0x3) * 8;
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/*
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* "DMA select" location is offset 0x28 in SD specification, but on
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* P5020 or P3041, it's located at 0x29.
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*/
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if (reg == SDHCI_HOST_CONTROL) {
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u32 dma_bits;
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if (spec_reg == SDHCI_HOST_CONTROL) {
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/*
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* If host control register is not standard, exit
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* this function
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*/
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if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
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return;
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return old_value;
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/* DMA select is 22,23 bits in Protocol Control Register */
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dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
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clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
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dma_bits);
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val &= ~SDHCI_CTRL_DMA_MASK;
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val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
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dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
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ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
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tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
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(old_value & SDHCI_CTRL_DMA_MASK);
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ret = (ret & (~0xff)) | tmp;
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
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ret &= ~ESDHC_HOST_CONTROL_RES;
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return ret;
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}
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
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if (reg == SDHCI_HOST_CONTROL)
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val &= ~ESDHC_HOST_CONTROL_RES;
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sdhci_be32bs_writeb(host, val, reg);
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ret = (old_value & (~(0xff << shift))) | (value << shift);
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return ret;
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}
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static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
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{
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u32 ret;
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u32 value;
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value = ioread32be(host->ioaddr + reg);
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ret = esdhc_readl_fixup(host, reg, value);
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return ret;
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}
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static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
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{
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u32 ret;
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u32 value;
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value = ioread32(host->ioaddr + reg);
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ret = esdhc_readl_fixup(host, reg, value);
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return ret;
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}
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static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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u32 value;
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int base = reg & ~0x3;
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value = ioread32be(host->ioaddr + base);
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ret = esdhc_readw_fixup(host, reg, value);
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return ret;
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}
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static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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u32 value;
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int base = reg & ~0x3;
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value = ioread32(host->ioaddr + base);
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ret = esdhc_readw_fixup(host, reg, value);
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return ret;
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}
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static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
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{
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u8 ret;
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u32 value;
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int base = reg & ~0x3;
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value = ioread32be(host->ioaddr + base);
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ret = esdhc_readb_fixup(host, reg, value);
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return ret;
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}
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static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
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{
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u8 ret;
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u32 value;
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int base = reg & ~0x3;
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value = ioread32(host->ioaddr + base);
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ret = esdhc_readb_fixup(host, reg, value);
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return ret;
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}
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static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
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{
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u32 value;
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value = esdhc_writel_fixup(host, reg, val, 0);
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iowrite32be(value, host->ioaddr + reg);
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}
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static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
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{
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u32 value;
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value = esdhc_writel_fixup(host, reg, val, 0);
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iowrite32(value, host->ioaddr + reg);
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}
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static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
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{
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int base = reg & ~0x3;
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u32 value;
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u32 ret;
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value = ioread32be(host->ioaddr + base);
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ret = esdhc_writew_fixup(host, reg, val, value);
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if (reg != SDHCI_TRANSFER_MODE)
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iowrite32be(ret, host->ioaddr + base);
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}
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static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
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{
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int base = reg & ~0x3;
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u32 value;
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u32 ret;
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value = ioread32(host->ioaddr + base);
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ret = esdhc_writew_fixup(host, reg, val, value);
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if (reg != SDHCI_TRANSFER_MODE)
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iowrite32(ret, host->ioaddr + base);
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}
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static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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u32 value;
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u32 ret;
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value = ioread32be(host->ioaddr + base);
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ret = esdhc_writeb_fixup(host, reg, val, value);
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iowrite32be(ret, host->ioaddr + base);
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}
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static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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u32 value;
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u32 ret;
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value = ioread32(host->ioaddr + base);
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ret = esdhc_writeb_fixup(host, reg, val, value);
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iowrite32(ret, host->ioaddr + base);
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}
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/*
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@ -149,19 +345,17 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
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* For Continue, apply soft reset for data(SYSCTL[RSTD]);
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* and re-issue the entire read transaction from beginning.
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*/
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static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask)
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static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
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{
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u32 tmp;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_esdhc *esdhc = pltfm_host->priv;
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bool applicable;
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dma_addr_t dmastart;
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dma_addr_t dmanow;
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tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
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tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
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applicable = (intmask & SDHCI_INT_DATA_END) &&
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(intmask & SDHCI_INT_BLK_GAP) &&
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(tmp == VENDOR_V_23);
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(intmask & SDHCI_INT_BLK_GAP) &&
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(esdhc->vendor_ver == VENDOR_V_23);
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if (!applicable)
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return;
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@ -179,7 +373,11 @@ static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask)
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static int esdhc_of_enable_dma(struct sdhci_host *host)
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{
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setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
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u32 value;
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value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
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value |= ESDHC_DMA_SNOOP;
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sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
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return 0;
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}
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@ -199,6 +397,8 @@ static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
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static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_esdhc *esdhc = pltfm_host->priv;
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int pre_div = 1;
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int div = 1;
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u32 temp;
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@ -209,9 +409,7 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
|
|||
return;
|
||||
|
||||
/* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
|
||||
temp = esdhc_readw(host, SDHCI_HOST_VERSION);
|
||||
temp = (temp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
|
||||
if (temp < VENDOR_V_23)
|
||||
if (esdhc->vendor_ver < VENDOR_V_23)
|
||||
pre_div = 2;
|
||||
|
||||
/* Workaround to reduce the clock frequency for p1010 esdhc */
|
||||
|
|
@ -247,39 +445,26 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
|
|||
mdelay(1);
|
||||
}
|
||||
|
||||
static void esdhc_of_platform_init(struct sdhci_host *host)
|
||||
{
|
||||
u32 vvn;
|
||||
|
||||
vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
|
||||
vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
|
||||
if (vvn == VENDOR_V_22)
|
||||
host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
|
||||
|
||||
if (vvn > VENDOR_V_22)
|
||||
host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
|
||||
}
|
||||
|
||||
static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
|
||||
{
|
||||
u32 ctrl;
|
||||
|
||||
ctrl = sdhci_readl(host, ESDHC_PROCTL);
|
||||
ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
|
||||
switch (width) {
|
||||
case MMC_BUS_WIDTH_8:
|
||||
ctrl = ESDHC_CTRL_8BITBUS;
|
||||
ctrl |= ESDHC_CTRL_8BITBUS;
|
||||
break;
|
||||
|
||||
case MMC_BUS_WIDTH_4:
|
||||
ctrl = ESDHC_CTRL_4BITBUS;
|
||||
ctrl |= ESDHC_CTRL_4BITBUS;
|
||||
break;
|
||||
|
||||
default:
|
||||
ctrl = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL,
|
||||
ESDHC_CTRL_BUSWIDTH_MASK, ctrl);
|
||||
sdhci_writel(host, ctrl, ESDHC_PROCTL);
|
||||
}
|
||||
|
||||
static void esdhc_reset(struct sdhci_host *host, u8 mask)
|
||||
|
|
@ -290,32 +475,13 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
|
|||
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
||||
}
|
||||
|
||||
static const struct sdhci_ops sdhci_esdhc_ops = {
|
||||
.read_l = esdhc_readl,
|
||||
.read_w = esdhc_readw,
|
||||
.read_b = esdhc_readb,
|
||||
.write_l = esdhc_writel,
|
||||
.write_w = esdhc_writew,
|
||||
.write_b = esdhc_writeb,
|
||||
.set_clock = esdhc_of_set_clock,
|
||||
.enable_dma = esdhc_of_enable_dma,
|
||||
.get_max_clock = esdhc_of_get_max_clock,
|
||||
.get_min_clock = esdhc_of_get_min_clock,
|
||||
.platform_init = esdhc_of_platform_init,
|
||||
.adma_workaround = esdhci_of_adma_workaround,
|
||||
.set_bus_width = esdhc_pltfm_set_bus_width,
|
||||
.reset = esdhc_reset,
|
||||
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static u32 esdhc_proctl;
|
||||
static int esdhc_of_suspend(struct device *dev)
|
||||
{
|
||||
struct sdhci_host *host = dev_get_drvdata(dev);
|
||||
|
||||
esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
|
||||
esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
|
||||
|
||||
return sdhci_suspend_host(host);
|
||||
}
|
||||
|
|
@ -328,9 +494,8 @@ static int esdhc_of_resume(struct device *dev)
|
|||
if (ret == 0) {
|
||||
/* Isn't this already done by sdhci_resume_host() ? --rmk */
|
||||
esdhc_of_enable_dma(host);
|
||||
sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
|
||||
sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -343,30 +508,92 @@ static const struct dev_pm_ops esdhc_pmops = {
|
|||
#define ESDHC_PMOPS NULL
|
||||
#endif
|
||||
|
||||
static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
|
||||
/*
|
||||
* card detection could be handled via GPIO
|
||||
* eSDHC cannot support End Attribute in NOP ADMA descriptor
|
||||
*/
|
||||
static const struct sdhci_ops sdhci_esdhc_be_ops = {
|
||||
.read_l = esdhc_be_readl,
|
||||
.read_w = esdhc_be_readw,
|
||||
.read_b = esdhc_be_readb,
|
||||
.write_l = esdhc_be_writel,
|
||||
.write_w = esdhc_be_writew,
|
||||
.write_b = esdhc_be_writeb,
|
||||
.set_clock = esdhc_of_set_clock,
|
||||
.enable_dma = esdhc_of_enable_dma,
|
||||
.get_max_clock = esdhc_of_get_max_clock,
|
||||
.get_min_clock = esdhc_of_get_min_clock,
|
||||
.adma_workaround = esdhc_of_adma_workaround,
|
||||
.set_bus_width = esdhc_pltfm_set_bus_width,
|
||||
.reset = esdhc_reset,
|
||||
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
||||
};
|
||||
|
||||
static const struct sdhci_ops sdhci_esdhc_le_ops = {
|
||||
.read_l = esdhc_le_readl,
|
||||
.read_w = esdhc_le_readw,
|
||||
.read_b = esdhc_le_readb,
|
||||
.write_l = esdhc_le_writel,
|
||||
.write_w = esdhc_le_writew,
|
||||
.write_b = esdhc_le_writeb,
|
||||
.set_clock = esdhc_of_set_clock,
|
||||
.enable_dma = esdhc_of_enable_dma,
|
||||
.get_max_clock = esdhc_of_get_max_clock,
|
||||
.get_min_clock = esdhc_of_get_min_clock,
|
||||
.adma_workaround = esdhc_of_adma_workaround,
|
||||
.set_bus_width = esdhc_pltfm_set_bus_width,
|
||||
.reset = esdhc_reset,
|
||||
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
||||
};
|
||||
|
||||
static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
|
||||
.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
|
||||
| SDHCI_QUIRK_NO_CARD_NO_RESET
|
||||
| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
|
||||
.ops = &sdhci_esdhc_ops,
|
||||
.ops = &sdhci_esdhc_be_ops,
|
||||
};
|
||||
|
||||
static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
|
||||
.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
|
||||
| SDHCI_QUIRK_NO_CARD_NO_RESET
|
||||
| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
|
||||
.ops = &sdhci_esdhc_le_ops,
|
||||
};
|
||||
|
||||
static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
|
||||
{
|
||||
struct sdhci_pltfm_host *pltfm_host;
|
||||
struct sdhci_esdhc *esdhc;
|
||||
u16 host_ver;
|
||||
|
||||
pltfm_host = sdhci_priv(host);
|
||||
esdhc = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_esdhc),
|
||||
GFP_KERNEL);
|
||||
|
||||
host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
|
||||
esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
|
||||
SDHCI_VENDOR_VER_SHIFT;
|
||||
esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
|
||||
|
||||
pltfm_host->priv = esdhc;
|
||||
}
|
||||
|
||||
static int sdhci_esdhc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sdhci_host *host;
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
host = sdhci_pltfm_init(pdev, &sdhci_esdhc_pdata, 0);
|
||||
np = pdev->dev.of_node;
|
||||
|
||||
if (of_get_property(np, "little-endian", NULL))
|
||||
host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 0);
|
||||
else
|
||||
host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 0);
|
||||
|
||||
if (IS_ERR(host))
|
||||
return PTR_ERR(host);
|
||||
|
||||
esdhc_init(pdev, host);
|
||||
|
||||
sdhci_get_of_property(pdev);
|
||||
|
||||
np = pdev->dev.of_node;
|
||||
if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
|
||||
of_device_is_compatible(np, "fsl,p5020-esdhc") ||
|
||||
of_device_is_compatible(np, "fsl,p4080-esdhc") ||
|
||||
|
|
|
|||
Loading…
Reference in New Issue