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ALSA: hda - only sync BCLK to the display clock for Haswell & Broadwell 

Only Intel Haswell and Broadwell have a separate HD-A controller (PCI device 3)
for display audio, which needs to get 24MHz HD-A link BCLK from the variable
display core clock through vendor specific registers EM4 & EM5. Other platforms
(Baytrail, Braswell and Skylake) don't have this feature.

So this patch checks the PCI device ID of the controller in haswell_set_bclk()
and only sync BCLK for HSW and BDW.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Mengdong Lin 2015-04-20 17:33:57 +08:00 committed by Takashi Iwai
parent 9476d369d7
commit f4c1a311d8
1 changed files with 6 additions and 0 deletions
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6
sound/pci/hda/hda_i915.c
View File

@ -55,6 +55,12 @@ void haswell_set_bclk(struct hda_intel *hda)
int cdclk_freq; int cdclk_freq;
unsigned int bclk_m, bclk_n; unsigned int bclk_m, bclk_n;
struct i915_audio_component *acomp = &hda->audio_component; struct i915_audio_component *acomp = &hda->audio_component;
struct pci_dev *pci = hda->chip.pci;
/* Only Haswell/Broadwell need set BCLK */
if (pci->device != 0x0a0c && pci->device != 0x0c0c
&& pci->device != 0x0d0c && pci->device != 0x160c)
return;
if (!acomp->ops) if (!acomp->ops)
return; return;