[media] media: imx: Add MIPI CSI-2 Receiver subdev driver
Adds MIPI CSI-2 Receiver subdev driver. This subdev is required for sensors with a MIPI CSI2 interface. - Switch from the v4l2_of_ APIs to the v4l2_fwnode_ APIs. - Add the function csi2ipu_gasket_init() to initialize the gasket at s_power(ON). The gasket needs to be programmed with the correct color component ordering to handle UYVY vs. YUYV ordered mbus formats from sensors. Note that the description of the CSI2IPU_GASKET register in the i.MX6 reference manual is wrong w.r.t bit 2 (the manual refers to this register as CSI2_SW_RST): setting bit 2 selects YUYV order, not UYVY. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Steve Longerbeam
Mauro Carvalho Chehab
parent
f0d9c8924e
commit
f5138526e4
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@ -9,3 +9,4 @@ obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx-media-vdic.o
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obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx-media-ic.o
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obj-$(CONFIG_VIDEO_IMX_CSI) += imx-media-csi.o
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obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-mipi-csi2.o
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@ -0,0 +1,697 @@
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/*
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* MIPI CSI-2 Receiver Subdev for Freescale i.MX6 SOC.
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*
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* Copyright (c) 2012-2017 Mentor Graphics Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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#include "imx-media.h"
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/*
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* there must be 5 pads: 1 input pad from sensor, and
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* the 4 virtual channel output pads
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*/
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#define CSI2_SINK_PAD 0
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#define CSI2_NUM_SINK_PADS 1
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#define CSI2_NUM_SRC_PADS 4
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#define CSI2_NUM_PADS 5
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/*
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* The default maximum bit-rate per lane in Mbps, if the
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* source subdev does not provide V4L2_CID_LINK_FREQ.
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*/
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#define CSI2_DEFAULT_MAX_MBPS 849
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struct csi2_dev {
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struct device *dev;
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struct v4l2_subdev sd;
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struct media_pad pad[CSI2_NUM_PADS];
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struct clk *dphy_clk;
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struct clk *pllref_clk;
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struct clk *pix_clk; /* what is this? */
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void __iomem *base;
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struct v4l2_fwnode_bus_mipi_csi2 bus;
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/* lock to protect all members below */
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struct mutex lock;
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struct v4l2_mbus_framefmt format_mbus;
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int stream_count;
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struct v4l2_subdev *src_sd;
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bool sink_linked[CSI2_NUM_SRC_PADS];
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};
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#define DEVICE_NAME "imx6-mipi-csi2"
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/* Register offsets */
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#define CSI2_VERSION 0x000
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#define CSI2_N_LANES 0x004
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#define CSI2_PHY_SHUTDOWNZ 0x008
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#define CSI2_DPHY_RSTZ 0x00c
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#define CSI2_RESETN 0x010
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#define CSI2_PHY_STATE 0x014
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#define PHY_STOPSTATEDATA_BIT 4
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#define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n))
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#define PHY_RXCLKACTIVEHS BIT(8)
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#define PHY_RXULPSCLKNOT BIT(9)
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#define PHY_STOPSTATECLK BIT(10)
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#define CSI2_DATA_IDS_1 0x018
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#define CSI2_DATA_IDS_2 0x01c
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#define CSI2_ERR1 0x020
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#define CSI2_ERR2 0x024
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#define CSI2_MSK1 0x028
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#define CSI2_MSK2 0x02c
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#define CSI2_PHY_TST_CTRL0 0x030
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#define PHY_TESTCLR BIT(0)
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#define PHY_TESTCLK BIT(1)
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#define CSI2_PHY_TST_CTRL1 0x034
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#define PHY_TESTEN BIT(16)
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/*
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* i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is
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* not part of the MIPI CSI-2 core, but its registers fall in the
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* same register map range.
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*/
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#define CSI2IPU_GASKET 0xf00
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#define CSI2IPU_YUV422_YUYV BIT(2)
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static inline struct csi2_dev *sd_to_dev(struct v4l2_subdev *sdev)
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{
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return container_of(sdev, struct csi2_dev, sd);
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}
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/*
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* The required sequence of MIPI CSI-2 startup as specified in the i.MX6
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* reference manual is as follows:
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*
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* 1. Deassert presetn signal (global reset).
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* It's not clear what this "global reset" signal is (maybe APB
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* global reset), but in any case this step would be probably
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* be carried out during driver load in csi2_probe().
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*
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* 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state.
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* This must be carried out by the MIPI sensor's s_power(ON) subdev
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* op.
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*
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* 3. D-PHY initialization.
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* 4. CSI2 Controller programming (Set N_LANES, deassert PHY_SHUTDOWNZ,
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* deassert PHY_RSTZ, deassert CSI2_RESETN).
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* 5. Read the PHY status register (PHY_STATE) to confirm that all data and
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* clock lanes of the D-PHY are in LP-11 state.
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* 6. Configure the MIPI Camera Sensor to start transmitting a clock on the
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* D-PHY clock lane.
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* 7. CSI2 Controller programming - Read the PHY status register (PHY_STATE)
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* to confirm that the D-PHY is receiving a clock on the D-PHY clock lane.
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*
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* All steps 3 through 7 are carried out by csi2_s_stream(ON) here. Step
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* 6 is accomplished by calling the source subdev's s_stream(ON) between
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* steps 5 and 7.
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*/
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static void csi2_enable(struct csi2_dev *csi2, bool enable)
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{
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if (enable) {
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writel(0x1, csi2->base + CSI2_PHY_SHUTDOWNZ);
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writel(0x1, csi2->base + CSI2_DPHY_RSTZ);
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writel(0x1, csi2->base + CSI2_RESETN);
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} else {
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writel(0x0, csi2->base + CSI2_PHY_SHUTDOWNZ);
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writel(0x0, csi2->base + CSI2_DPHY_RSTZ);
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writel(0x0, csi2->base + CSI2_RESETN);
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}
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}
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static void csi2_set_lanes(struct csi2_dev *csi2)
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{
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int lanes = csi2->bus.num_data_lanes;
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writel(lanes - 1, csi2->base + CSI2_N_LANES);
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}
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static void dw_mipi_csi2_phy_write(struct csi2_dev *csi2,
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u32 test_code, u32 test_data)
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{
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/* Clear PHY test interface */
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writel(PHY_TESTCLR, csi2->base + CSI2_PHY_TST_CTRL0);
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writel(0x0, csi2->base + CSI2_PHY_TST_CTRL1);
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writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
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/* Raise test interface strobe signal */
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writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
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/* Configure address write on falling edge and lower strobe signal */
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writel(PHY_TESTEN | test_code, csi2->base + CSI2_PHY_TST_CTRL1);
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writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
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/* Configure data write on rising edge and raise strobe signal */
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writel(test_data, csi2->base + CSI2_PHY_TST_CTRL1);
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writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
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/* Clear strobe signal */
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writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
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}
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/*
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* This table is based on the table documented at
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* https://community.nxp.com/docs/DOC-94312. It assumes
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* a 27MHz D-PHY pll reference clock.
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*/
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static const struct {
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u32 max_mbps;
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u32 hsfreqrange_sel;
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} hsfreq_map[] = {
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{ 90, 0x00}, {100, 0x20}, {110, 0x40}, {125, 0x02},
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{140, 0x22}, {150, 0x42}, {160, 0x04}, {180, 0x24},
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{200, 0x44}, {210, 0x06}, {240, 0x26}, {250, 0x46},
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{270, 0x08}, {300, 0x28}, {330, 0x48}, {360, 0x2a},
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{400, 0x4a}, {450, 0x0c}, {500, 0x2c}, {550, 0x0e},
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{600, 0x2e}, {650, 0x10}, {700, 0x30}, {750, 0x12},
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{800, 0x32}, {850, 0x14}, {900, 0x34}, {950, 0x54},
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{1000, 0x74},
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};
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static int max_mbps_to_hsfreqrange_sel(u32 max_mbps)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(hsfreq_map); i++)
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if (hsfreq_map[i].max_mbps > max_mbps)
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return hsfreq_map[i].hsfreqrange_sel;
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return -EINVAL;
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}
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static int csi2_dphy_init(struct csi2_dev *csi2)
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{
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struct v4l2_ctrl *ctrl;
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u32 mbps_per_lane;
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int sel;
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ctrl = v4l2_ctrl_find(csi2->src_sd->ctrl_handler,
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V4L2_CID_LINK_FREQ);
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if (!ctrl)
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mbps_per_lane = CSI2_DEFAULT_MAX_MBPS;
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else
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mbps_per_lane = DIV_ROUND_UP_ULL(2 * ctrl->qmenu_int[ctrl->val],
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USEC_PER_SEC);
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sel = max_mbps_to_hsfreqrange_sel(mbps_per_lane);
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if (sel < 0)
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return sel;
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dw_mipi_csi2_phy_write(csi2, 0x44, sel);
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return 0;
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}
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/*
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* Waits for ultra-low-power state on D-PHY clock lane. This is currently
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* unused and may not be needed at all, but keep around just in case.
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*/
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static int __maybe_unused csi2_dphy_wait_ulp(struct csi2_dev *csi2)
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{
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u32 reg;
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int ret;
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/* wait for ULP on clock lane */
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ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
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!(reg & PHY_RXULPSCLKNOT), 0, 500000);
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if (ret) {
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v4l2_err(&csi2->sd, "ULP timeout, phy_state = 0x%08x\n", reg);
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return ret;
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}
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/* wait until no errors on bus */
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ret = readl_poll_timeout(csi2->base + CSI2_ERR1, reg,
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reg == 0x0, 0, 500000);
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if (ret) {
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v4l2_err(&csi2->sd, "stable bus timeout, err1 = 0x%08x\n", reg);
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return ret;
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}
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return 0;
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}
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/* Waits for low-power LP-11 state on data and clock lanes. */
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static int csi2_dphy_wait_stopstate(struct csi2_dev *csi2)
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{
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u32 mask, reg;
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int ret;
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mask = PHY_STOPSTATECLK |
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((csi2->bus.num_data_lanes - 1) << PHY_STOPSTATEDATA_BIT);
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ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
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(reg & mask) == mask, 0, 500000);
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if (ret) {
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v4l2_err(&csi2->sd, "LP-11 timeout, phy_state = 0x%08x\n", reg);
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return ret;
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}
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return 0;
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}
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/* Wait for active clock on the clock lane. */
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static int csi2_dphy_wait_clock_lane(struct csi2_dev *csi2)
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{
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u32 reg;
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int ret;
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ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
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(reg & PHY_RXCLKACTIVEHS), 0, 500000);
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if (ret) {
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v4l2_err(&csi2->sd, "clock lane timeout, phy_state = 0x%08x\n",
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reg);
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return ret;
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}
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return 0;
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}
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/* Setup the i.MX CSI2IPU Gasket */
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static void csi2ipu_gasket_init(struct csi2_dev *csi2)
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{
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u32 reg = 0;
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switch (csi2->format_mbus.code) {
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case MEDIA_BUS_FMT_YUYV8_2X8:
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case MEDIA_BUS_FMT_YUYV8_1X16:
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reg = CSI2IPU_YUV422_YUYV;
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break;
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default:
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break;
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}
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writel(reg, csi2->base + CSI2IPU_GASKET);
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}
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static int csi2_start(struct csi2_dev *csi2)
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{
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int ret;
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ret = clk_prepare_enable(csi2->pix_clk);
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if (ret)
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return ret;
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/* setup the gasket */
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csi2ipu_gasket_init(csi2);
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/* Step 3 */
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ret = csi2_dphy_init(csi2);
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if (ret)
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goto err_disable_clk;
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/* Step 4 */
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csi2_set_lanes(csi2);
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csi2_enable(csi2, true);
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/* Step 5 */
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ret = csi2_dphy_wait_stopstate(csi2);
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if (ret)
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goto err_assert_reset;
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/* Step 6 */
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ret = v4l2_subdev_call(csi2->src_sd, video, s_stream, 1);
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ret = (ret && ret != -ENOIOCTLCMD) ? ret : 0;
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if (ret)
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goto err_assert_reset;
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/* Step 7 */
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ret = csi2_dphy_wait_clock_lane(csi2);
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if (ret)
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goto err_stop_upstream;
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return 0;
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err_stop_upstream:
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v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
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err_assert_reset:
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csi2_enable(csi2, false);
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err_disable_clk:
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clk_disable_unprepare(csi2->pix_clk);
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return ret;
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}
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static void csi2_stop(struct csi2_dev *csi2)
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{
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/* stop upstream */
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v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
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csi2_enable(csi2, false);
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clk_disable_unprepare(csi2->pix_clk);
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}
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/*
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* V4L2 subdev operations.
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*/
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static int csi2_s_stream(struct v4l2_subdev *sd, int enable)
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{
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struct csi2_dev *csi2 = sd_to_dev(sd);
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int i, ret = 0;
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mutex_lock(&csi2->lock);
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if (!csi2->src_sd) {
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ret = -EPIPE;
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goto out;
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}
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for (i = 0; i < CSI2_NUM_SRC_PADS; i++) {
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if (csi2->sink_linked[i])
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break;
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}
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if (i >= CSI2_NUM_SRC_PADS) {
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ret = -EPIPE;
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goto out;
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}
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/*
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* enable/disable streaming only if stream_count is
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* going from 0 to 1 / 1 to 0.
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*/
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if (csi2->stream_count != !enable)
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goto update_count;
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dev_dbg(csi2->dev, "stream %s\n", enable ? "ON" : "OFF");
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if (enable)
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ret = csi2_start(csi2);
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else
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csi2_stop(csi2);
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if (ret)
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goto out;
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update_count:
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csi2->stream_count += enable ? 1 : -1;
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WARN_ON(csi2->stream_count < 0);
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out:
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mutex_unlock(&csi2->lock);
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return ret;
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}
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static int csi2_link_setup(struct media_entity *entity,
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const struct media_pad *local,
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const struct media_pad *remote, u32 flags)
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{
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struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
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struct csi2_dev *csi2 = sd_to_dev(sd);
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struct v4l2_subdev *remote_sd;
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int ret = 0;
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dev_dbg(csi2->dev, "link setup %s -> %s", remote->entity->name,
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local->entity->name);
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|
||||
remote_sd = media_entity_to_v4l2_subdev(remote->entity);
|
||||
|
||||
mutex_lock(&csi2->lock);
|
||||
|
||||
if (local->flags & MEDIA_PAD_FL_SOURCE) {
|
||||
if (flags & MEDIA_LNK_FL_ENABLED) {
|
||||
if (csi2->sink_linked[local->index - 1]) {
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
csi2->sink_linked[local->index - 1] = true;
|
||||
} else {
|
||||
csi2->sink_linked[local->index - 1] = false;
|
||||
}
|
||||
} else {
|
||||
if (flags & MEDIA_LNK_FL_ENABLED) {
|
||||
if (csi2->src_sd) {
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
csi2->src_sd = remote_sd;
|
||||
} else {
|
||||
csi2->src_sd = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
mutex_unlock(&csi2->lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int csi2_get_fmt(struct v4l2_subdev *sd,
|
||||
struct v4l2_subdev_pad_config *cfg,
|
||||
struct v4l2_subdev_format *sdformat)
|
||||
{
|
||||
struct csi2_dev *csi2 = sd_to_dev(sd);
|
||||
struct v4l2_mbus_framefmt *fmt;
|
||||
|
||||
mutex_lock(&csi2->lock);
|
||||
|
||||
if (sdformat->which == V4L2_SUBDEV_FORMAT_TRY)
|
||||
fmt = v4l2_subdev_get_try_format(&csi2->sd, cfg,
|
||||
sdformat->pad);
|
||||
else
|
||||
fmt = &csi2->format_mbus;
|
||||
|
||||
sdformat->format = *fmt;
|
||||
|
||||
mutex_unlock(&csi2->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csi2_set_fmt(struct v4l2_subdev *sd,
|
||||
struct v4l2_subdev_pad_config *cfg,
|
||||
struct v4l2_subdev_format *sdformat)
|
||||
{
|
||||
struct csi2_dev *csi2 = sd_to_dev(sd);
|
||||
int ret = 0;
|
||||
|
||||
if (sdformat->pad >= CSI2_NUM_PADS)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&csi2->lock);
|
||||
|
||||
if (csi2->stream_count > 0) {
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Output pads mirror active input pad, no limits on input pads */
|
||||
if (sdformat->pad != CSI2_SINK_PAD)
|
||||
sdformat->format = csi2->format_mbus;
|
||||
|
||||
if (sdformat->which == V4L2_SUBDEV_FORMAT_TRY)
|
||||
cfg->try_fmt = sdformat->format;
|
||||
else
|
||||
csi2->format_mbus = sdformat->format;
|
||||
out:
|
||||
mutex_unlock(&csi2->lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* retrieve our pads parsed from the OF graph by the media device
|
||||
*/
|
||||
static int csi2_registered(struct v4l2_subdev *sd)
|
||||
{
|
||||
struct csi2_dev *csi2 = sd_to_dev(sd);
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < CSI2_NUM_PADS; i++) {
|
||||
csi2->pad[i].flags = (i == CSI2_SINK_PAD) ?
|
||||
MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
|
||||
}
|
||||
|
||||
/* set a default mbus format */
|
||||
ret = imx_media_init_mbus_fmt(&csi2->format_mbus,
|
||||
640, 480, 0, V4L2_FIELD_NONE, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return media_entity_pads_init(&sd->entity, CSI2_NUM_PADS, csi2->pad);
|
||||
}
|
||||
|
||||
static const struct media_entity_operations csi2_entity_ops = {
|
||||
.link_setup = csi2_link_setup,
|
||||
.link_validate = v4l2_subdev_link_validate,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_video_ops csi2_video_ops = {
|
||||
.s_stream = csi2_s_stream,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
|
||||
.get_fmt = csi2_get_fmt,
|
||||
.set_fmt = csi2_set_fmt,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_ops csi2_subdev_ops = {
|
||||
.video = &csi2_video_ops,
|
||||
.pad = &csi2_pad_ops,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
|
||||
.registered = csi2_registered,
|
||||
};
|
||||
|
||||
static int csi2_parse_endpoints(struct csi2_dev *csi2)
|
||||
{
|
||||
struct device_node *node = csi2->dev->of_node;
|
||||
struct device_node *epnode;
|
||||
struct v4l2_fwnode_endpoint ep;
|
||||
|
||||
epnode = of_graph_get_endpoint_by_regs(node, 0, -1);
|
||||
if (!epnode) {
|
||||
v4l2_err(&csi2->sd, "failed to get sink endpoint node\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
v4l2_fwnode_endpoint_parse(of_fwnode_handle(epnode), &ep);
|
||||
of_node_put(epnode);
|
||||
|
||||
if (ep.bus_type != V4L2_MBUS_CSI2) {
|
||||
v4l2_err(&csi2->sd, "invalid bus type, must be MIPI CSI2\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
csi2->bus = ep.bus.mipi_csi2;
|
||||
|
||||
dev_dbg(csi2->dev, "data lanes: %d\n", csi2->bus.num_data_lanes);
|
||||
dev_dbg(csi2->dev, "flags: 0x%08x\n", csi2->bus.flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csi2_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct csi2_dev *csi2;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
csi2 = devm_kzalloc(&pdev->dev, sizeof(*csi2), GFP_KERNEL);
|
||||
if (!csi2)
|
||||
return -ENOMEM;
|
||||
|
||||
csi2->dev = &pdev->dev;
|
||||
|
||||
v4l2_subdev_init(&csi2->sd, &csi2_subdev_ops);
|
||||
v4l2_set_subdevdata(&csi2->sd, &pdev->dev);
|
||||
csi2->sd.internal_ops = &csi2_internal_ops;
|
||||
csi2->sd.entity.ops = &csi2_entity_ops;
|
||||
csi2->sd.dev = &pdev->dev;
|
||||
csi2->sd.owner = THIS_MODULE;
|
||||
csi2->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
|
||||
strcpy(csi2->sd.name, DEVICE_NAME);
|
||||
csi2->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
|
||||
csi2->sd.grp_id = IMX_MEDIA_GRP_ID_CSI2;
|
||||
|
||||
ret = csi2_parse_endpoints(csi2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
csi2->pllref_clk = devm_clk_get(&pdev->dev, "ref");
|
||||
if (IS_ERR(csi2->pllref_clk)) {
|
||||
v4l2_err(&csi2->sd, "failed to get pll reference clock\n");
|
||||
ret = PTR_ERR(csi2->pllref_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
csi2->dphy_clk = devm_clk_get(&pdev->dev, "dphy");
|
||||
if (IS_ERR(csi2->dphy_clk)) {
|
||||
v4l2_err(&csi2->sd, "failed to get dphy clock\n");
|
||||
ret = PTR_ERR(csi2->dphy_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
csi2->pix_clk = devm_clk_get(&pdev->dev, "pix");
|
||||
if (IS_ERR(csi2->pix_clk)) {
|
||||
v4l2_err(&csi2->sd, "failed to get pixel clock\n");
|
||||
ret = PTR_ERR(csi2->pix_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
v4l2_err(&csi2->sd, "failed to get platform resources\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
csi2->base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
|
||||
if (!csi2->base) {
|
||||
v4l2_err(&csi2->sd, "failed to map CSI-2 registers\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
mutex_init(&csi2->lock);
|
||||
|
||||
ret = clk_prepare_enable(csi2->pllref_clk);
|
||||
if (ret) {
|
||||
v4l2_err(&csi2->sd, "failed to enable pllref_clk\n");
|
||||
goto rmmutex;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(csi2->dphy_clk);
|
||||
if (ret) {
|
||||
v4l2_err(&csi2->sd, "failed to enable dphy_clk\n");
|
||||
goto pllref_off;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, &csi2->sd);
|
||||
|
||||
ret = v4l2_async_register_subdev(&csi2->sd);
|
||||
if (ret)
|
||||
goto dphy_off;
|
||||
|
||||
return 0;
|
||||
|
||||
dphy_off:
|
||||
clk_disable_unprepare(csi2->dphy_clk);
|
||||
pllref_off:
|
||||
clk_disable_unprepare(csi2->pllref_clk);
|
||||
rmmutex:
|
||||
mutex_destroy(&csi2->lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int csi2_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
|
||||
struct csi2_dev *csi2 = sd_to_dev(sd);
|
||||
|
||||
v4l2_async_unregister_subdev(sd);
|
||||
clk_disable_unprepare(csi2->dphy_clk);
|
||||
clk_disable_unprepare(csi2->pllref_clk);
|
||||
mutex_destroy(&csi2->lock);
|
||||
media_entity_cleanup(&sd->entity);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id csi2_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx6-mipi-csi2", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, csi2_dt_ids);
|
||||
|
||||
static struct platform_driver csi2_driver = {
|
||||
.driver = {
|
||||
.name = DEVICE_NAME,
|
||||
.of_match_table = csi2_dt_ids,
|
||||
},
|
||||
.probe = csi2_probe,
|
||||
.remove = csi2_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(csi2_driver);
|
||||
|
||||
MODULE_DESCRIPTION("i.MX5/6 MIPI CSI-2 Receiver driver");
|
||||
MODULE_AUTHOR("Steve Longerbeam <steve_longerbeam@mentor.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue