x86/mce/AMD: Add system physical address translation for AMD Fam17h
The Unified Memory Controllers (UMCs) on Fam17h log a normalized address
in their MCA_ADDR registers. We need to convert that normalized address
to a system physical address in order to support a few facilities:
1) To offline poisoned pages in DRAM proactively in the deferred error
handler.
2) To print sysaddr and page info for DRAM ECC errors in EDAC.
[ Boris: fixes/cleanups ontop:
* hi_addr_offset = 0 - no need for that branch. Stick it all under the
HiAddrOffsetEn case. It confines hi_addr_offset's declaration too.
* Move variables to the innermost scope they're used at so that we save
on stack and not blow it up immediately on function entry.
* Do not modify *sys_addr prematurely - we want to not exit early and
have modified *sys_addr some, which callers get to see. We either
convert to a sys_addr or we don't do anything. And we signal that with
the retval of the function.
* Rename label out -> out_err - because it is the error path.
* No need to pr_err of the conversion failed case: imagine a
sparsely-populated machine with UMCs which don't have DIMMs. Callers
should look at the retval instead and issue a printk only when really
necessary. No need for useless info in dmesg.
* s/temp_reg/tmp/ and other variable names shortening => shorter code.
* Use BIT() everywhere.
* Make error messages more informative.
* Small build fix for the !CONFIG_X86_MCE_AMD case.
* ... and more minor cleanups.
]
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20161122111133.mjzpvzhf7o7yl2oa@pd.tnic
[ Typo fixes. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Yazen Ghannam
Ingo Molnar
parent
ddfe43cdc0
commit
f5382de9d4
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@ -1025,7 +1025,7 @@ config X86_MCE_INTEL
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config X86_MCE_AMD
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def_bool y
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prompt "AMD MCE features"
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depends on X86_MCE && X86_LOCAL_APIC
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depends on X86_MCE && X86_LOCAL_APIC && AMD_NB
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---help---
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Additional support for AMD specific MCE features such as
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the DRAM Error Threshold.
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@ -252,8 +252,10 @@ static inline void cmci_recheck(void) {}
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
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#endif
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int mce_available(struct cpuinfo_x86 *c);
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@ -553,6 +553,206 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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deferred_error_interrupt_enable(c);
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}
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int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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{
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u64 dram_base_addr, dram_limit_addr, dram_hole_base;
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/* We start from the normalized address */
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u64 ret_addr = norm_addr;
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u32 tmp;
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u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
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u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
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u8 intlv_addr_sel, intlv_addr_bit;
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u8 num_intlv_bits, hashed_bit;
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u8 lgcy_mmio_hole_en, base = 0;
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u8 cs_mask, cs_id = 0;
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bool hash_enabled = false;
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/* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
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if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
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goto out_err;
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/* Remove HiAddrOffset from normalized address, if enabled: */
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if (tmp & BIT(0)) {
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u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
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if (norm_addr >= hi_addr_offset) {
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ret_addr -= hi_addr_offset;
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base = 1;
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}
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}
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/* Read D18F0x110 (DramBaseAddress). */
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if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
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goto out_err;
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/* Check if address range is valid. */
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if (!(tmp & BIT(0))) {
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pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
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__func__, tmp);
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goto out_err;
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}
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lgcy_mmio_hole_en = tmp & BIT(1);
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intlv_num_chan = (tmp >> 4) & 0xF;
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intlv_addr_sel = (tmp >> 8) & 0x7;
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dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16;
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/* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
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if (intlv_addr_sel > 3) {
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pr_err("%s: Invalid interleave address select %d.\n",
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__func__, intlv_addr_sel);
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goto out_err;
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}
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/* Read D18F0x114 (DramLimitAddress). */
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if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
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goto out_err;
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intlv_num_sockets = (tmp >> 8) & 0x1;
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intlv_num_dies = (tmp >> 10) & 0x3;
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dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
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intlv_addr_bit = intlv_addr_sel + 8;
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/* Re-use intlv_num_chan by setting it equal to log2(#channels) */
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switch (intlv_num_chan) {
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case 0: intlv_num_chan = 0; break;
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case 1: intlv_num_chan = 1; break;
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case 3: intlv_num_chan = 2; break;
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case 5: intlv_num_chan = 3; break;
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case 7: intlv_num_chan = 4; break;
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case 8: intlv_num_chan = 1;
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hash_enabled = true;
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break;
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default:
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pr_err("%s: Invalid number of interleaved channels %d.\n",
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__func__, intlv_num_chan);
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goto out_err;
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}
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num_intlv_bits = intlv_num_chan;
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if (intlv_num_dies > 2) {
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pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
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__func__, intlv_num_dies);
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goto out_err;
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}
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num_intlv_bits += intlv_num_dies;
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/* Add a bit if sockets are interleaved. */
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num_intlv_bits += intlv_num_sockets;
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/* Assert num_intlv_bits <= 4 */
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if (num_intlv_bits > 4) {
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pr_err("%s: Invalid interleave bits %d.\n",
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__func__, num_intlv_bits);
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goto out_err;
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}
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if (num_intlv_bits > 0) {
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u64 temp_addr_x, temp_addr_i, temp_addr_y;
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u8 die_id_bit, sock_id_bit, cs_fabric_id;
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/*
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* Read FabricBlockInstanceInformation3_CS[BlockFabricID].
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* This is the fabric id for this coherent slave. Use
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* umc/channel# as instance id of the coherent slave
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* for FICAA.
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*/
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if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
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goto out_err;
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cs_fabric_id = (tmp >> 8) & 0xFF;
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die_id_bit = 0;
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/* If interleaved over more than 1 channel: */
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if (intlv_num_chan) {
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die_id_bit = intlv_num_chan;
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cs_mask = (1 << die_id_bit) - 1;
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cs_id = cs_fabric_id & cs_mask;
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}
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sock_id_bit = die_id_bit;
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/* Read D18F1x208 (SystemFabricIdMask). */
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if (intlv_num_dies || intlv_num_sockets)
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if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
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goto out_err;
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/* If interleaved over more than 1 die. */
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if (intlv_num_dies) {
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sock_id_bit = die_id_bit + intlv_num_dies;
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die_id_shift = (tmp >> 24) & 0xF;
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die_id_mask = (tmp >> 8) & 0xFF;
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cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
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}
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/* If interleaved over more than 1 socket. */
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if (intlv_num_sockets) {
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socket_id_shift = (tmp >> 28) & 0xF;
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socket_id_mask = (tmp >> 16) & 0xFF;
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cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
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}
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/*
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* The pre-interleaved address consists of XXXXXXIIIYYYYY
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* where III is the ID for this CS, and XXXXXXYYYYY are the
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* address bits from the post-interleaved address.
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* "num_intlv_bits" has been calculated to tell us how many "I"
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* bits there are. "intlv_addr_bit" tells us how many "Y" bits
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* there are (where "I" starts).
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*/
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temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
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temp_addr_i = (cs_id << intlv_addr_bit);
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temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
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ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
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}
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/* Add dram base address */
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ret_addr += dram_base_addr;
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/* If legacy MMIO hole enabled */
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if (lgcy_mmio_hole_en) {
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if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
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goto out_err;
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dram_hole_base = tmp & GENMASK(31, 24);
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if (ret_addr >= dram_hole_base)
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ret_addr += (BIT_ULL(32) - dram_hole_base);
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}
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if (hash_enabled) {
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/* Save some parentheses and grab ls-bit at the end. */
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hashed_bit = (ret_addr >> 12) ^
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(ret_addr >> 18) ^
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(ret_addr >> 21) ^
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(ret_addr >> 30) ^
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cs_id;
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hashed_bit &= BIT(0);
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if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
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ret_addr ^= BIT(intlv_addr_bit);
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}
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/* Is calculated system address is above DRAM limit address? */
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if (ret_addr > dram_limit_addr)
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goto out_err;
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*sys_addr = ret_addr;
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return 0;
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out_err:
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
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static void
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__log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc)
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{
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