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drm/amd/display: add per pipe dppclk 

v2: Fix commit title

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2018-02-12 15:19:20 -05:00 committed by Alex Deucher
parent 8ff15a8fcc
commit f553e68102
5 changed files with 28 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
View File

@ -996,7 +996,7 @@ bool dcn_validate_bandwidth(
dc->debug.min_disp_clk_khz;
}
context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
context->bw.dcn.calc_clk.max_dppclk_khz = (int)(v->dppclk * 1000);
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

13
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
View File

@ -361,21 +361,22 @@ void context_clock_trace(
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d\n"
CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n"
"dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
context->bw.dcn.calc_clk.dppclk_div,
context->bw.dcn.calc_clk.max_dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz,
context->bw.dcn.calc_clk.socclk_khz,
context->bw.dcn.calc_clk.dram_ccm_us,
context->bw.dcn.calc_clk.min_active_dram_ccm_us);
CLOCK_TRACE("Calculated: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d\n"
CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n"
"dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
context->bw.dcn.calc_clk.dppclk_div,
context->bw.dcn.calc_clk.max_dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz,

6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
View File

@ -432,14 +432,12 @@ void dpp1_dppclk_control(
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
if (enable) {
if (dpp->tf_mask->DPPCLK_RATE_CONTROL) {
if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
REG_UPDATE_2(DPP_CONTROL,
DPPCLK_RATE_CONTROL, dppclk_div,
DPP_CLOCK_ENABLE, 1);
} else {
ASSERT(dppclk_div == false);
else
REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
}
} else
REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
}

9
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -1684,12 +1684,13 @@ static void update_dchubp_dpp(
if (plane_state->update_flags.bits.full_update) {
dpp->funcs->dpp_dppclk_control(
dpp,
context->bw.dcn.calc_clk.dppclk_div,
context->bw.dcn.calc_clk.max_dppclk_khz <
context->bw.dcn.calc_clk.dispclk_khz,
true);
dc->current_state->bw.dcn.cur_clk.dppclk_div =
context->bw.dcn.calc_clk.dppclk_div;
context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
dc->current_state->bw.dcn.cur_clk.max_dppclk_khz =
context->bw.dcn.calc_clk.max_dppclk_khz;
context->bw.dcn.cur_clk.max_dppclk_khz = context->bw.dcn.calc_clk.max_dppclk_khz;
}
/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG

15
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -177,6 +177,15 @@ struct resource_pool {
const struct resource_caps *res_cap;
};
struct dcn_fe_clocks {
int dppclk_khz;
};
struct dcn_fe_bandwidth {
struct dcn_fe_clocks calc;
struct dcn_fe_clocks cur;
};
struct stream_resource {
struct output_pixel_processor *opp;
struct timing_generator *tg;
@ -195,6 +204,8 @@ struct plane_resource {
struct transform *xfm;
struct dpp *dpp;
uint8_t mpcc_inst;
struct dcn_fe_bandwidth bw;
};
struct pipe_ctx {
@ -247,9 +258,9 @@ struct dce_bw_output {
struct dcn_bw_clocks {
int dispclk_khz;
int dppclk_khz;
bool dppclk_div;
int max_dppclk_khz;
int dcfclk_khz;
int socclk_khz;
int dcfclk_deep_sleep_khz;
int fclk_khz;
int dram_ccm_us;