SoCFPGA DTS updates for v5.1
- Add SMMU node for Stratix10 - Add vendor prefix fo Novtech - Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA - Add missing reset properties for all IP on Cyclone5 and Arria10 -----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAlxYYAAUHGRpbmd1eWVu QGtlcm5lbC5vcmcACgkQGZQEC4GjKPSfPA//a013n1vCV9Wz6RsbXNRODXzhV6FN 9uPWAdbkuWrCvDFAH+9s/0nMwxAj8f1HCEK9J07CPRcjcLPO7iHfIUeJ4lbCNCXZ 1ZuLDdK0Y4GjziJ4xlUP0JvUpJXtRKo+XDXVC+jNAMQy6wQpsEYdEwpeTPo94jrv X0Zait3PeaY6ai6ImzV4QOYYmZ9GhRHjNY/Hc8jSsZeMWk+sMWygExlUngXlpO8c dvK1Z4dfhrRZyJ/ewjjb/D0eekq8XiIfGmI4A2Cox3A73XAmtPEL3MT57BbPnq7f jmNmlh7yRrxZHVErSt0dJTOJ6dNx+McuuwSmDL1vR19M44JUbVOjLjDUEwA7tSmr eQXVhGuYHfxgJT0CeEBIHJAxPZfTqy68IijZYXv4aWimFdsbeAtraY7PKeZ/TnOP 3Aa9GDSks5NsAGVR5AltiNRmZujyQktbcNU8TcNt8tc19Kub8Q9GVhsmPUIKEov8 oAeXq4xbvGe6Ike6cfR1H+P14mgpbxJSZwGQoqky1T3lWqFBhl/93/ixpzt5jMWX 96tHA7VuZ7+in3BoqzHNxZ2PWpHScd3UScLxzxFEotW2nCofXCLCVkW+Zl8xWLa9 eu5GXE0ZzA04Elaagj2MM/rTsIgWFWqROq4A3Za6k5AB7quThr1yMoL+5Q5keOlO 4xAhCKudZb74BS4= =8OgV -----END PGP SIGNATURE----- Merge tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.1 - Add SMMU node for Stratix10 - Add vendor prefix fo Novtech - Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA - Add missing reset properties for all IP on Cyclone5 and Arria10 * tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: update more missing reset properties ARM: dts: socfpga: update missing reset property peripherals ARM: dts: Add support for 96Boards Chameleon96 board dt-bindings: vendor-prefixes: Add Novtech Vendor Prefix arm64: dts: stratix10: Add Stratix10 SMMU support Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
f5691ad172
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@ -274,6 +274,7 @@ nintendo Nintendo
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nlt NLT Technologies, Ltd.
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nokia Nokia
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nordic Nordic Semiconductor
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novtech NovTech, Inc.
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nutsboard NutsBoard
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nuvoton Nuvoton Technology Corporation
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nvd New Vision Display
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|
|
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@ -924,6 +924,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
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socfpga_arria10_socdk_nand.dtb \
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socfpga_arria10_socdk_qspi.dtb \
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socfpga_arria10_socdk_sdmmc.dtb \
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socfpga_cyclone5_chameleon96.dtb \
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socfpga_cyclone5_mcvevk.dtb \
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socfpga_cyclone5_socdk.dtb \
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socfpga_cyclone5_de0_nano_soc.dtb \
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@ -84,6 +84,7 @@ pdma: pdma@ffe01000 {
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#dma-requests = <32>;
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clocks = <&l4_main_clk>;
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clock-names = "apb_pclk";
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resets = <&rst DMA_RESET>;
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};
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};
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@ -100,6 +101,7 @@ can0: can@ffc00000 {
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reg = <0xffc00000 0x1000>;
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interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
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clocks = <&can0_clk>;
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resets = <&rst CAN0_RESET>;
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status = "disabled";
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};
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@ -108,6 +110,7 @@ can1: can@ffc01000 {
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reg = <0xffc01000 0x1000>;
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interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
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clocks = <&can1_clk>;
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resets = <&rst CAN1_RESET>;
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status = "disabled";
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};
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@ -585,6 +588,7 @@ gpio0: gpio@ff708000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff708000 0x1000>;
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clocks = <&l4_mp_clk>;
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resets = <&rst GPIO0_RESET>;
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status = "disabled";
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porta: gpio-controller@0 {
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@ -605,6 +609,7 @@ gpio1: gpio@ff709000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff709000 0x1000>;
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clocks = <&l4_mp_clk>;
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resets = <&rst GPIO1_RESET>;
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status = "disabled";
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portb: gpio-controller@0 {
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@ -625,6 +630,7 @@ gpio2: gpio@ff70a000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff70a000 0x1000>;
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clocks = <&l4_mp_clk>;
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resets = <&rst GPIO2_RESET>;
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status = "disabled";
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portc: gpio-controller@0 {
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@ -735,6 +741,7 @@ mmc: dwmmc0@ff704000 {
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#size-cells = <0>;
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clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
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clock-names = "biu", "ciu";
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resets = <&rst SDMMC_RESET>;
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status = "disabled";
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};
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@ -748,6 +755,7 @@ nand0: nand@ff900000 {
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interrupts = <0x0 0x90 0x4>;
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clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
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clock-names = "nand", "nand_x", "ecc";
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resets = <&rst NAND_RESET>;
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status = "disabled";
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};
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@ -767,6 +775,7 @@ qspi: spi@ff705000 {
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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clocks = <&qspi_clk>;
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resets = <&rst QSPI_RESET>;
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status = "disabled";
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};
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@ -785,6 +794,7 @@ scu: snoop-control-unit@fffec000 {
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sdr: sdr@ffc25000 {
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compatible = "altr,sdr-ctl", "syscon";
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reg = <0xffc25000 0x1000>;
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resets = <&rst SDR_RESET>;
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};
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sdramedac {
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@ -801,6 +811,7 @@ spi0: spi@fff00000 {
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interrupts = <0 154 4>;
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num-cs = <4>;
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clocks = <&spi_m_clk>;
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resets = <&rst SPIM0_RESET>;
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status = "disabled";
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};
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@ -812,6 +823,7 @@ spi1: spi@fff01000 {
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interrupts = <0 155 4>;
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num-cs = <4>;
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clocks = <&spi_m_clk>;
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resets = <&rst SPIM1_RESET>;
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status = "disabled";
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};
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@ -878,6 +890,7 @@ uart0: serial0@ffc02000 {
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dmas = <&pdma 28>,
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<&pdma 29>;
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dma-names = "tx", "rx";
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resets = <&rst UART0_RESET>;
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};
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uart1: serial1@ffc03000 {
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@ -890,6 +903,7 @@ uart1: serial1@ffc03000 {
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dmas = <&pdma 30>,
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<&pdma 31>;
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dma-names = "tx", "rx";
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resets = <&rst UART1_RESET>;
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};
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usbphy0: usbphy {
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@ -929,6 +943,7 @@ watchdog0: watchdog@ffd02000 {
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reg = <0xffd02000 0x1000>;
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interrupts = <0 171 4>;
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clocks = <&osc1>;
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resets = <&rst L4WD0_RESET>;
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status = "disabled";
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};
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@ -937,6 +952,7 @@ watchdog1: watchdog@ffd03000 {
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reg = <0xffd03000 0x1000>;
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interrupts = <0 172 4>;
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clocks = <&osc1>;
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resets = <&rst L4WD1_RESET>;
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status = "disabled";
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};
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};
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@ -470,6 +470,7 @@ gmac2: ethernet@ff804000 {
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tx-fifo-depth = <4096>;
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rx-fifo-depth = <16384>;
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clocks = <&l4_mp_clk>;
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resets = <&rst EMAC2_RESET>;
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clock-names = "stmmaceth";
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snps,axi-config = <&socfpga_axi_setup>;
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status = "disabled";
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@ -480,6 +481,7 @@ gpio0: gpio@ffc02900 {
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02900 0x100>;
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resets = <&rst GPIO0_RESET>;
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status = "disabled";
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porta: gpio-controller@0 {
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@ -499,6 +501,7 @@ gpio1: gpio@ffc02a00 {
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02a00 0x100>;
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resets = <&rst GPIO1_RESET>;
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status = "disabled";
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portb: gpio-controller@0 {
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@ -518,6 +521,7 @@ gpio2: gpio@ffc02b00 {
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02b00 0x100>;
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resets = <&rst GPIO2_RESET>;
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status = "disabled";
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portc: gpio-controller@0 {
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@ -548,6 +552,7 @@ i2c0: i2c@ffc02200 {
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reg = <0xffc02200 0x100>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C0_RESET>;
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status = "disabled";
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};
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@ -558,6 +563,7 @@ i2c1: i2c@ffc02300 {
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reg = <0xffc02300 0x100>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C1_RESET>;
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status = "disabled";
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};
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@ -568,6 +574,7 @@ i2c2: i2c@ffc02400 {
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reg = <0xffc02400 0x100>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C2_RESET>;
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status = "disabled";
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};
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@ -578,6 +585,7 @@ i2c3: i2c@ffc02500 {
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reg = <0xffc02500 0x100>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C3_RESET>;
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status = "disabled";
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};
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@ -588,6 +596,7 @@ i2c4: i2c@ffc02600 {
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reg = <0xffc02600 0x100>;
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interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C4_RESET>;
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status = "disabled";
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};
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@ -600,6 +609,7 @@ spi0: spi@ffda4000 {
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num-cs = <4>;
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/*32bit_access;*/
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clocks = <&spi_m_clk>;
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resets = <&rst SPIM0_RESET>;
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status = "disabled";
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};
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@ -614,6 +624,7 @@ spi1: spi@ffda5000 {
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tx-dma-channel = <&pdma 16>;
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rx-dma-channel = <&pdma 17>;
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clocks = <&spi_m_clk>;
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resets = <&rst SPIM1_RESET>;
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status = "disabled";
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};
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@ -642,6 +653,7 @@ mmc: dwmmc0@ff808000 {
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fifo-depth = <0x400>;
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clocks = <&l4_mp_clk>, <&sdmmc_clk>;
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clock-names = "biu", "ciu";
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resets = <&rst SDMMC_RESET>;
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status = "disabled";
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};
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@ -655,6 +667,7 @@ nand: nand@ffb90000 {
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interrupts = <0 99 4>;
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clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
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clock-names = "nand", "nand_x", "ecc";
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resets = <&rst NAND_RESET>;
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status = "disabled";
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};
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@ -739,6 +752,7 @@ qspi: spi@ff809000 {
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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clocks = <&qspi_clk>;
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resets = <&rst QSPI_RESET>;
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status = "disabled";
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};
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@ -815,6 +829,7 @@ uart0: serial0@ffc02000 {
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&l4_sp_clk>;
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resets = <&rst UART0_RESET>;
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status = "disabled";
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};
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@ -825,6 +840,7 @@ uart1: serial1@ffc02100 {
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&l4_sp_clk>;
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resets = <&rst UART1_RESET>;
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status = "disabled";
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};
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@ -865,6 +881,7 @@ watchdog0: watchdog@ffd00200 {
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reg = <0xffd00200 0x100>;
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interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sys_free_clk>;
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resets = <&rst L4WD0_RESET>;
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status = "disabled";
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};
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@ -873,6 +890,7 @@ watchdog1: watchdog@ffd00300 {
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reg = <0xffd00300 0x100>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sys_free_clk>;
|
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resets = <&rst L4WD1_RESET>;
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||||
status = "disabled";
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||||
};
|
||||
};
|
||||
|
|
|
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|
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@ -0,0 +1,130 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Device Tree file for the Chameleon96
|
||||
*
|
||||
* Copyright (c) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Novetech Chameleon96";
|
||||
compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x20000000>; /* 512MB */
|
||||
};
|
||||
|
||||
regulator_3_3v: 3-3-v-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user_led1 {
|
||||
label = "green:user1";
|
||||
gpios = <&porta 14 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
user_led2 {
|
||||
label = "green:user2";
|
||||
gpios = <&porta 22 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
user_led3 {
|
||||
label = "green:user3";
|
||||
gpios = <&porta 25 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
user_led4 {
|
||||
label = "green:user4";
|
||||
gpios = <&portb 3 GPIO_ACTIVE_LOW>;
|
||||
panic-indicator;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
/* On Low speed expansion */
|
||||
label = "LS-I2C0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
/* On Low speed expansion */
|
||||
label = "LS-I2C1";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
/* On High speed expansion */
|
||||
label = "HS-I2C2";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
vmmc-supply = <®ulator_3_3v>;
|
||||
vqmmc-supply = <®ulator_3_3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
/* On High speed expansion */
|
||||
label = "HS-SPI1";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
/* On Low speed expansion */
|
||||
label = "LS-SPI0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
/* On Low speed expansion */
|
||||
label = "LS-UART1";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
/* On Low speed expansion */
|
||||
label = "LS-UART0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -161,6 +161,7 @@ gmac0: ethernet@ff800000 {
|
|||
tx-fifo-depth = <16384>;
|
||||
rx-fifo-depth = <16384>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
iommus = <&smmu 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -177,6 +178,7 @@ gmac1: ethernet@ff802000 {
|
|||
tx-fifo-depth = <16384>;
|
||||
rx-fifo-depth = <16384>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
iommus = <&smmu 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -193,6 +195,7 @@ gmac2: ethernet@ff804000 {
|
|||
tx-fifo-depth = <16384>;
|
||||
rx-fifo-depth = <16384>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
iommus = <&smmu 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -303,6 +306,7 @@ mmc: dwmmc0@ff808000 {
|
|||
clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
|
||||
<&clkmgr STRATIX10_SDMMC_CLK>;
|
||||
clock-names = "biu", "ciu";
|
||||
iommus = <&smmu 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -336,6 +340,29 @@ rst: rstmgr@ffd11000 {
|
|||
reg = <0xffd11000 0x1000>;
|
||||
};
|
||||
|
||||
smmu: iommu@fa000000 {
|
||||
compatible = "arm,mmu-500", "arm,smmu-v2";
|
||||
reg = <0xfa000000 0x40000>;
|
||||
#global-interrupts = <2>;
|
||||
#iommu-cells = <1>;
|
||||
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
|
||||
clock-names = "iommu";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 128 4>, /* Global Secure Fault */
|
||||
<0 129 4>, /* Global Non-secure Fault */
|
||||
/* Non-secure Context Interrupts (32) */
|
||||
<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
|
||||
<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
|
||||
<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
|
||||
<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
|
||||
<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
|
||||
<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
|
||||
<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
|
||||
<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
|
||||
stream-match-mask = <0x7ff0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@ffda4000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -445,6 +472,7 @@ usb0: usb@ffb00000 {
|
|||
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
|
||||
reset-names = "dwc2", "dwc2-ecc";
|
||||
clocks = <&clkmgr STRATIX10_USB_CLK>;
|
||||
iommus = <&smmu 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -457,6 +485,7 @@ usb1: usb@ffb40000 {
|
|||
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
|
||||
reset-names = "dwc2", "dwc2-ecc";
|
||||
clocks = <&clkmgr STRATIX10_USB_CLK>;
|
||||
iommus = <&smmu 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue