iwlwifi: add support of FPGA fw
Load FW according to NIC type, taking into account simulation, if exists. This is determined by a prph register. Signed-off-by: Tzipi Peres <tzipi.peres@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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@ -75,11 +75,14 @@
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#define IWL_A000_JF_FW_PRE "iwlwifi-Qu-a0-jf-b0-"
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#define IWL_A000_HR_FW_PRE "iwlwifi-Qu-a0-hr-a0-"
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#define IWL_A000_HR_CDB_FW_PRE "iwlwifi-QuIcp-z0-hrcdb-a0-"
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#define IWL_A000_HR_F0_FW_PRE "iwlwifi-QuQnj-f0-hr-a0-"
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#define IWL_A000_HR_MODULE_FIRMWARE(api) \
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IWL_A000_HR_FW_PRE "-" __stringify(api) ".ucode"
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#define IWL_A000_JF_MODULE_FIRMWARE(api) \
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IWL_A000_JF_FW_PRE "-" __stringify(api) ".ucode"
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#define IWL_A000_HR_QNJ_MODULE_FIRMWARE(api) \
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IWL_A000_HR_F0_FW_PRE "-" __stringify(api) ".ucode"
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#define NVM_HW_SECTION_NUM_FAMILY_A000 10
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@ -168,5 +171,16 @@ const struct iwl_cfg iwla000_2ax_cfg_hr = {
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,
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};
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const struct iwl_cfg iwla000_2ax_cfg_qnj_hr = {
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.name = "Intel(R) Dual Band Wireless AX a000",
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.fw_name_pre = IWL_A000_HR_F0_FW_PRE,
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IWL_DEVICE_A000,
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.ht_params = &iwl_a000_ht_params,
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.nvm_ver = IWL_A000_NVM_VERSION,
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.nvm_calib_ver = IWL_A000_TX_POWER_VERSION,
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.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,
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};
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MODULE_FIRMWARE(IWL_A000_HR_MODULE_FIRMWARE(IWL_A000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_A000_JF_MODULE_FIRMWARE(IWL_A000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_A000_HR_QNJ_MODULE_FIRMWARE(IWL_A000_UCODE_API_MAX));
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@ -463,6 +463,7 @@ extern const struct iwl_cfg iwla000_2ac_cfg_hr;
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extern const struct iwl_cfg iwla000_2ac_cfg_hr_cdb;
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extern const struct iwl_cfg iwla000_2ac_cfg_jf;
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extern const struct iwl_cfg iwla000_2ax_cfg_hr;
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extern const struct iwl_cfg iwla000_2ax_cfg_qnj_hr;
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#endif /* CONFIG_IWLMVM */
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#endif /* __IWL_CONFIG_H__ */
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@ -404,6 +404,12 @@ enum aux_misc_master1_en {
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#define SB_CPU_2_STATUS 0xA01E34
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#define UMAG_SB_CPU_1_STATUS 0xA038C0
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#define UMAG_SB_CPU_2_STATUS 0xA038C4
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#define UMAG_GEN_HW_STATUS 0xA038C8
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/* For UMAG_GEN_HW_STATUS reg check */
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enum {
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UMAG_GEN_HW_IS_FPGA = BIT(1),
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};
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/* FW chicken bits */
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#define LMPM_CHICK 0xA01FF8
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@ -3137,7 +3137,18 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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iwl_set_bit(trans, CSR_HOST_CHICKEN,
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CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
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#if IS_ENABLED(CONFIG_IWLMVM)
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trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
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if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
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u32 hw_status;
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hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
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if (hw_status & UMAG_GEN_HW_IS_FPGA)
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trans->cfg = &iwla000_2ax_cfg_qnj_hr;
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else
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trans->cfg = &iwla000_2ac_cfg_hr;
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}
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#endif
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iwl_pcie_set_interrupt_capa(pdev, trans);
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trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
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