drm/i915: Move init_clock_gating() back to where it was
Apparently setting up a bunch of GT registers before we've properly initialized the rest of the GT hardware leads to these setting being lost. So looks like I broke HSW with commitb7048ea12f("drm/i915: Do .init_clock_gating() earlier to avoid it clobbering watermarks") by doing init_clock_gating() too early. This should actually affect other platforms as well, but apparently not to such a great degree. What I was ultimately after in that commit was to move the ilk_init_lp_watermarks() call earlier. So let's undo the damage and move init_clock_gating() back to where it was, and call ilk_init_lp_watermarks() just before the watermark state readout. This highlights how fragile and messed up our init order really is. I wonder why we even initialize the display before gem. The opposite order would make much more sense to me... v2: Keep WaRsPkgCStateDisplayPMReq:hsw early as it really must be done before all planes might get disabled. Cc: stable@vger.kernel.org Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mark Janes <mark.a.janes@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reported-by: Mark Janes <mark.a.janes@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103549 Fixes:b7048ea12f("drm/i915: Do .init_clock_gating() earlier to avoid it clobbering watermarks") References: https://lists.freedesktop.org/archives/intel-gfx/2017-November/145432.html Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171108133555.14091-1-ville.syrjala@linux.intel.com Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Ville Syrjälä
parent
1ab22356b3
commit
f72b84c677
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@ -3674,6 +3674,7 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
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intel_pps_unlock_regs_wa(dev_priv);
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intel_modeset_init_hw(dev);
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intel_init_clock_gating(dev_priv);
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spin_lock_irq(&dev_priv->irq_lock);
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if (dev_priv->display.hpd_irq_setup)
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@ -14363,8 +14364,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
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intel_update_cdclk(dev_priv);
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intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
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dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
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intel_init_clock_gating(dev_priv);
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}
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/*
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@ -15094,6 +15093,15 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
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struct intel_encoder *encoder;
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int i;
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if (IS_HASWELL(dev_priv)) {
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/*
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* WaRsPkgCStateDisplayPMReq:hsw
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* System hang if this isn't done before disabling all planes!
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*/
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I915_WRITE(CHICKEN_PAR1_1,
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I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
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}
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intel_modeset_readout_hw_state(dev);
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/* HW state is read out, now we need to sanitize this mess. */
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@ -15191,6 +15199,8 @@ void intel_modeset_gem_init(struct drm_device *dev)
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intel_init_gt_powersave(dev_priv);
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intel_init_clock_gating(dev_priv);
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intel_setup_overlay(dev_priv);
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}
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@ -5754,12 +5754,30 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
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mutex_unlock(&dev_priv->wm.wm_mutex);
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}
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/*
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* FIXME should probably kill this and improve
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* the real watermark readout/sanitation instead
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*/
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static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
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{
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I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
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I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
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I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
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/*
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* Don't touch WM1S_LP_EN here.
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* Doing so could cause underruns.
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*/
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}
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void ilk_wm_get_hw_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct ilk_wm_values *hw = &dev_priv->wm.hw;
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struct drm_crtc *crtc;
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ilk_init_lp_watermarks(dev_priv);
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for_each_crtc(dev, crtc)
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ilk_pipe_wm_get_hw_state(crtc);
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@ -8213,18 +8231,6 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
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}
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}
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static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
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{
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I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
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I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
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I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
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/*
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* Don't touch WM1S_LP_EN here.
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* Doing so could cause underruns.
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*/
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}
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static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
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{
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uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
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@ -8258,8 +8264,6 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
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(I915_READ(DISP_ARB_CTL) |
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DISP_FBC_WM_DIS));
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ilk_init_lp_watermarks(dev_priv);
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/*
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* Based on the document from hardware guys the following bits
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* should be set unconditionally in order to enable FBC.
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@ -8372,8 +8376,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN6_GT_MODE,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
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ilk_init_lp_watermarks(dev_priv);
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I915_WRITE(CACHE_MODE_0,
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_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
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@ -8600,8 +8602,6 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
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I915_GTT_PAGE_SIZE_2M);
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enum pipe pipe;
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ilk_init_lp_watermarks(dev_priv);
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/* WaSwitchSolVfFArbitrationPriority:bdw */
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I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
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@ -8652,8 +8652,6 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
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static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
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{
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ilk_init_lp_watermarks(dev_priv);
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/* L3 caching of data atomics doesn't work -- disable it. */
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I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
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I915_WRITE(HSW_ROW_CHICKEN3,
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@ -8697,10 +8695,6 @@ static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
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/* WaSwitchSolVfFArbitrationPriority:hsw */
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I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
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/* WaRsPkgCStateDisplayPMReq:hsw */
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I915_WRITE(CHICKEN_PAR1_1,
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I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
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lpt_init_clock_gating(dev_priv);
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}
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@ -8708,8 +8702,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
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{
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uint32_t snpcr;
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ilk_init_lp_watermarks(dev_priv);
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I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
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/* WaDisableEarlyCull:ivb */
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