KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable
Enable the VGIC operation by properly initialising the registers in the hypervisor GIC interface. Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
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@ -206,9 +206,18 @@ void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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GICH_VMCR_PRIMASK_SHIFT;
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}
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/* not yet implemented */
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void vgic_v2_enable(struct kvm_vcpu *vcpu)
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{
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/*
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* By forcing VMCR to zero, the GIC will restore the binary
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* points to their reset values. Anything else resets to zero
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* anyway.
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*/
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vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
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vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
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/* Get the show on the road... */
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vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
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}
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/* check for overlapping regions and for regions crossing the end of memory */
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@ -186,9 +186,30 @@ void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
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}
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/* not yet implemented */
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void vgic_v3_enable(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
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/*
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* By forcing VMCR to zero, the GIC will restore the binary
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* points to their reset values. Anything else resets to zero
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* anyway.
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*/
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vgic_v3->vgic_vmcr = 0;
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vgic_v3->vgic_elrsr = ~0;
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/*
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* If we are emulating a GICv3, we do it in an non-GICv2-compatible
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* way, so we force SRE to 1 to demonstrate this to the guest.
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* This goes with the spec allowing the value to be RAO/WI.
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*/
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if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
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vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
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else
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vgic_v3->vgic_sre = 0;
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/* Get the show on the road... */
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vgic_v3->vgic_hcr = ICH_HCR_EN;
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}
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/* check for overlapping regions and for regions crossing the end of memory */
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