spi: dw-mid: move to use core SPI DMA mappings
SPI core has a comprehensive function set to map and unmap a message when it's needed. This patch converts driver to use that advantage. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Andy Shevchenko
Mark Brown
parent
4d5ac1edfd
commit
f89a6d8f43
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@ -69,6 +69,7 @@ static int mid_spi_dma_init(struct dw_spi *dws)
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rxs->hs_mode = LNW_DMA_HW_HS;
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rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
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dws->rxchan->private = rxs;
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dws->master->dma_rx = dws->rxchan;
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/* 2. Init tx channel */
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dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
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@ -78,6 +79,7 @@ static int mid_spi_dma_init(struct dw_spi *dws)
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txs->hs_mode = LNW_DMA_HW_HS;
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txs->cfg_mode = LNW_DMA_MEM_TO_PER;
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dws->txchan->private = txs;
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dws->master->dma_tx = dws->txchan;
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dws->dma_inited = 1;
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return 0;
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@ -116,6 +118,17 @@ static irqreturn_t dma_transfer(struct dw_spi *dws)
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return IRQ_HANDLED;
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}
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static bool mid_spi_can_dma(struct spi_master *master, struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct dw_spi *dws = spi_master_get_devdata(master);
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if (!dws->dma_inited)
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return false;
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return xfer->len > dws->fifo_len;
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}
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static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
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if (dma_width == 1)
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return DMA_SLAVE_BUSWIDTH_1_BYTE;
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@ -139,12 +152,13 @@ static void dw_spi_dma_tx_done(void *arg)
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spi_finalize_current_transfer(dws->master);
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}
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
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struct spi_transfer *xfer)
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{
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struct dma_slave_config txconf;
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struct dma_async_tx_descriptor *txdesc;
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if (!dws->tx_dma)
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if (!xfer->tx_buf)
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return NULL;
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txconf.direction = DMA_MEM_TO_DEV;
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@ -156,13 +170,9 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
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dmaengine_slave_config(dws->txchan, &txconf);
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memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
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dws->tx_sgl.dma_address = dws->tx_dma;
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dws->tx_sgl.length = dws->len;
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txdesc = dmaengine_prep_slave_sg(dws->txchan,
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&dws->tx_sgl,
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1,
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xfer->tx_sg.sgl,
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xfer->tx_sg.nents,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc)
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@ -188,12 +198,13 @@ static void dw_spi_dma_rx_done(void *arg)
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spi_finalize_current_transfer(dws->master);
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}
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
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struct spi_transfer *xfer)
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{
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struct dma_slave_config rxconf;
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struct dma_async_tx_descriptor *rxdesc;
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if (!dws->rx_dma)
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if (!xfer->rx_buf)
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return NULL;
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rxconf.direction = DMA_DEV_TO_MEM;
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@ -205,13 +216,9 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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dmaengine_slave_config(dws->rxchan, &rxconf);
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memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
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dws->rx_sgl.dma_address = dws->rx_dma;
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dws->rx_sgl.length = dws->len;
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rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
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&dws->rx_sgl,
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1,
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xfer->rx_sg.sgl,
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xfer->rx_sg.nents,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!rxdesc)
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@ -223,16 +230,16 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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return rxdesc;
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}
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static int mid_spi_dma_setup(struct dw_spi *dws)
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static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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u16 dma_ctrl = 0;
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dw_writew(dws, DW_SPI_DMARDLR, 0xf);
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dw_writew(dws, DW_SPI_DMATDLR, 0x10);
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if (dws->tx_dma)
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if (xfer->tx_buf)
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dma_ctrl |= SPI_DMA_TDMAE;
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if (dws->rx_dma)
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if (xfer->rx_buf)
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dma_ctrl |= SPI_DMA_RDMAE;
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dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
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@ -244,15 +251,15 @@ static int mid_spi_dma_setup(struct dw_spi *dws)
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return 0;
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}
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static int mid_spi_dma_transfer(struct dw_spi *dws)
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static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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struct dma_async_tx_descriptor *txdesc, *rxdesc;
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/* Prepare the TX dma transfer */
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txdesc = dw_spi_dma_prepare_tx(dws);
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txdesc = dw_spi_dma_prepare_tx(dws, xfer);
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/* Prepare the RX dma transfer */
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rxdesc = dw_spi_dma_prepare_rx(dws);
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rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
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/* rx must be started before tx due to spi instinct */
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if (rxdesc) {
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@ -286,6 +293,7 @@ static struct dw_spi_dma_ops mid_dma_ops = {
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.dma_init = mid_spi_dma_init,
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.dma_exit = mid_spi_dma_exit,
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.dma_setup = mid_spi_dma_setup,
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.can_dma = mid_spi_can_dma,
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.dma_transfer = mid_spi_dma_transfer,
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.dma_stop = mid_spi_dma_stop,
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};
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@ -217,32 +217,6 @@ static void dw_reader(struct dw_spi *dws)
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}
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}
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/*
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* Note: first step is the protocol driver prepares
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* a dma-capable memory, and this func just need translate
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* the virt addr to physical
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*/
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static int map_dma_buffers(struct spi_master *master,
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struct spi_device *spi, struct spi_transfer *transfer)
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{
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struct dw_spi *dws = spi_master_get_devdata(master);
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struct chip_data *chip = spi_get_ctldata(spi);
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if (!master->cur_msg->is_dma_mapped
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|| !dws->dma_inited
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|| !chip->enable_dma
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|| !dws->dma_ops)
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return 0;
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if (transfer->tx_dma)
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dws->tx_dma = transfer->tx_dma;
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if (transfer->rx_dma)
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dws->rx_dma = transfer->rx_dma;
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return 1;
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}
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static void int_error_stop(struct dw_spi *dws, const char *msg)
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{
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spi_reset_chip(dws);
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@ -322,11 +296,10 @@ static int dw_spi_transfer_one(struct spi_master *master,
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u32 cr0 = 0;
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int ret;
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dws->dma_mapped = 0;
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dws->n_bytes = chip->n_bytes;
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dws->dma_width = chip->dma_width;
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dws->rx_dma = transfer->rx_dma;
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dws->tx_dma = transfer->tx_dma;
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dws->tx = (void *)transfer->tx_buf;
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dws->tx_end = dws->tx + transfer->len;
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dws->rx = transfer->rx_buf;
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@ -386,7 +359,8 @@ static int dw_spi_transfer_one(struct spi_master *master,
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dw_writew(dws, DW_SPI_CTRL0, cr0);
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/* Check if current transfer is a DMA transaction */
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dws->dma_mapped = map_dma_buffers(master, spi, transfer);
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if (master->can_dma && master->can_dma(master, spi, transfer))
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dws->dma_mapped = master->cur_msg_mapped;
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/* For poll mode just disable all interrupts */
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spi_mask_intr(dws, 0xff);
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@ -396,7 +370,7 @@ static int dw_spi_transfer_one(struct spi_master *master,
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* we only need set the TXEI IRQ, as TX/RX always happen syncronizely
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*/
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if (dws->dma_mapped) {
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ret = dws->dma_ops->dma_setup(dws);
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ret = dws->dma_ops->dma_setup(dws, transfer);
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if (ret < 0) {
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spi_enable_chip(dws, 1);
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return ret;
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@ -416,7 +390,7 @@ static int dw_spi_transfer_one(struct spi_master *master,
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spi_enable_chip(dws, 1);
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if (dws->dma_mapped) {
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ret = dws->dma_ops->dma_transfer(dws);
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ret = dws->dma_ops->dma_transfer(dws, transfer);
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if (ret < 0)
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return ret;
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}
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@ -470,8 +444,6 @@ static int dw_spi_setup(struct spi_device *spi)
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chip->rx_threshold = 0;
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chip->tx_threshold = 0;
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chip->enable_dma = chip_info->enable_dma;
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}
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if (spi->bits_per_word == 8) {
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@ -584,6 +556,8 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
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if (ret) {
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dev_warn(dev, "DMA init failed\n");
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dws->dma_inited = 0;
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} else {
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master->can_dma = dws->dma_ops->can_dma;
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}
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}
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@ -91,8 +91,10 @@ struct dw_spi;
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struct dw_spi_dma_ops {
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int (*dma_init)(struct dw_spi *dws);
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void (*dma_exit)(struct dw_spi *dws);
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int (*dma_setup)(struct dw_spi *dws);
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int (*dma_transfer)(struct dw_spi *dws);
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int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
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bool (*can_dma)(struct spi_master *master, struct spi_device *spi,
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struct spi_transfer *xfer);
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int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
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void (*dma_stop)(struct dw_spi *dws);
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};
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@ -117,20 +119,14 @@ struct dw_spi {
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void *rx;
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void *rx_end;
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int dma_mapped;
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dma_addr_t rx_dma;
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dma_addr_t tx_dma;
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size_t rx_map_len;
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size_t tx_map_len;
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u8 n_bytes; /* current is a 1/2 bytes op */
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u32 dma_width;
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irqreturn_t (*transfer_handler)(struct dw_spi *dws);
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/* Dma info */
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/* DMA info */
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int dma_inited;
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struct dma_chan *txchan;
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struct scatterlist tx_sgl;
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struct dma_chan *rxchan;
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struct scatterlist rx_sgl;
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unsigned long dma_chan_busy;
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struct device *dma_dev;
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dma_addr_t dma_addr; /* phy address of the Data register */
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@ -206,14 +202,13 @@ static inline void spi_reset_chip(struct dw_spi *dws)
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/*
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* Each SPI slave device to work with dw_api controller should
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* has such a structure claiming its working mode (PIO/DMA etc),
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* has such a structure claiming its working mode (poll or PIO/DMA),
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* which can be save in the "controller_data" member of the
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* struct spi_device.
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*/
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struct dw_spi_chip {
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u8 poll_mode; /* 1 for controller polling mode */
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u8 type; /* SPI/SSP/MicroWire */
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u8 enable_dma;
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void (*cs_control)(u32 command);
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};
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