KVM: arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler
Add a handler for reading/writing the guest's view of the ICC_IGRPEN1_EL1 register, which is located in the ICH_VMCR_EL2.VENG1 field. Tested-by: Alexander Graf <agraf@suse.de> Acked-by: David Daney <david.daney@cavium.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@linaro.org>
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@ -401,6 +401,23 @@ static unsigned int __hyp_text __vgic_v3_get_bpr1(u32 vmcr)
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return bpr;
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}
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static void __hyp_text __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
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}
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static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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u64 val = vcpu_get_reg(vcpu, rt);
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if (val & 1)
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vmcr |= ICH_VMCR_ENG1_MASK;
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else
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vmcr &= ~ICH_VMCR_ENG1_MASK;
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__vgic_v3_write_vmcr(vmcr);
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}
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static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
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@ -448,6 +465,12 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
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is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
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switch (sysreg) {
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case SYS_ICC_GRPEN1_EL1:
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if (is_read)
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fn = __vgic_v3_read_igrpen1;
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else
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fn = __vgic_v3_write_igrpen1;
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break;
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case SYS_ICC_BPR1_EL1:
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if (is_read)
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fn = __vgic_v3_read_bpr1;
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