MIPS: Add register definitions for VZ ASE registers
Add various register definitions to <asm/mipsregs.h> for the coprocessor zero registers in the VZ ASE, namely CP0_GuestCtl0, CP0_GuestCtl0Ext, CP0_GuestCtl1, CP0_GuestCtl2, CP0_GuestCtl3, and CP0_GTOffset. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13228/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan
Ralf Baechle
parent
9e575f7535
commit
f913e9ea39
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@ -55,8 +55,14 @@
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#define CP0_BADINSTR $8, 1
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#define CP0_COUNT $9
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#define CP0_ENTRYHI $10
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#define CP0_GUESTCTL1 $10, 4
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#define CP0_GUESTCTL2 $10, 5
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#define CP0_GUESTCTL3 $10, 6
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#define CP0_COMPARE $11
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#define CP0_GUESTCTL0EXT $11, 4
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#define CP0_STATUS $12
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#define CP0_GUESTCTL0 $12, 6
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#define CP0_GTOFFSET $12, 7
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#define CP0_CAUSE $13
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#define CP0_EPC $14
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#define CP0_PRID $15
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@ -740,6 +746,94 @@
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#define MIPS_PWCTL_PSN_SHIFT 0
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#define MIPS_PWCTL_PSN_MASK 0x0000003f
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/* GuestCtl0 fields */
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#define MIPS_GCTL0_GM_SHIFT 31
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#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
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#define MIPS_GCTL0_RI_SHIFT 30
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#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
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#define MIPS_GCTL0_MC_SHIFT 29
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#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
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#define MIPS_GCTL0_CP0_SHIFT 28
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#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
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#define MIPS_GCTL0_AT_SHIFT 26
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#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
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#define MIPS_GCTL0_GT_SHIFT 25
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#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
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#define MIPS_GCTL0_CG_SHIFT 24
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#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
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#define MIPS_GCTL0_CF_SHIFT 23
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#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
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#define MIPS_GCTL0_G1_SHIFT 22
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#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
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#define MIPS_GCTL0_G0E_SHIFT 19
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#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
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#define MIPS_GCTL0_PT_SHIFT 18
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#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
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#define MIPS_GCTL0_RAD_SHIFT 9
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#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
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#define MIPS_GCTL0_DRG_SHIFT 8
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#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
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#define MIPS_GCTL0_G2_SHIFT 7
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#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
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#define MIPS_GCTL0_GEXC_SHIFT 2
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#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
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#define MIPS_GCTL0_SFC2_SHIFT 1
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#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
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#define MIPS_GCTL0_SFC1_SHIFT 0
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#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
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/* GuestCtl0.AT Guest address translation control */
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#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
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#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
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/* GuestCtl0.GExcCode Hypervisor exception cause codes */
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#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
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#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
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#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
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#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
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#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
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#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
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#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
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/* GuestCtl0Ext fields */
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#define MIPS_GCTL0EXT_RPW_SHIFT 8
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#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
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#define MIPS_GCTL0EXT_NCC_SHIFT 6
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#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
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#define MIPS_GCTL0EXT_CGI_SHIFT 4
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#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
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#define MIPS_GCTL0EXT_FCD_SHIFT 3
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#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
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#define MIPS_GCTL0EXT_OG_SHIFT 2
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#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
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#define MIPS_GCTL0EXT_BG_SHIFT 1
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#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
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#define MIPS_GCTL0EXT_MG_SHIFT 0
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#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
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/* GuestCtl0Ext.RPW Root page walk configuration */
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#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
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#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
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#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
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/* GuestCtl0Ext.NCC Nested cache coherency attributes */
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#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
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#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
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/* GuestCtl1 fields */
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#define MIPS_GCTL1_ID_SHIFT 0
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#define MIPS_GCTL1_ID_WIDTH 8
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#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
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#define MIPS_GCTL1_RID_SHIFT 16
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#define MIPS_GCTL1_RID_WIDTH 8
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#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
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#define MIPS_GCTL1_EID_SHIFT 24
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#define MIPS_GCTL1_EID_WIDTH 8
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#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
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/* GuestID reserved for root context */
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#define MIPS_GCTL1_ROOT_GUESTID 0
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/* CDMMBase register bit definitions */
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#define MIPS_CDMMBASE_SIZE_SHIFT 0
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#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
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@ -1270,9 +1364,21 @@ do { \
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#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
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#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
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#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
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#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
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#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
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#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
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#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
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#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
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#define read_c0_compare() __read_32bit_c0_register($11, 0)
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#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
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#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
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#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
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#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
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#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
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@ -1283,6 +1389,12 @@ do { \
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#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
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#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
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#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
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#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
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#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
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#define read_c0_cause() __read_32bit_c0_register($13, 0)
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#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
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@ -2111,6 +2223,11 @@ __BUILD_SET_C0(intcontrol)
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__BUILD_SET_C0(intctl)
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__BUILD_SET_C0(srsmap)
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__BUILD_SET_C0(pagegrain)
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__BUILD_SET_C0(guestctl0)
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__BUILD_SET_C0(guestctl0ext)
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__BUILD_SET_C0(guestctl1)
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__BUILD_SET_C0(guestctl2)
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__BUILD_SET_C0(guestctl3)
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__BUILD_SET_C0(brcm_config_0)
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__BUILD_SET_C0(brcm_bus_pll)
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__BUILD_SET_C0(brcm_reset)
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