net/mlx5_core: Add setting ATOMIC endian mode
HW is capable of 2 requestor endianness modes for standard 8 Bytes atomic: BE (0x0) and host endianness (0x1). Read the supported modes from hca atomic capabilities and configure HW to host endianness mode if supported. Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com> Reviewed-by: Yishai Hadas <yishaih@mellanox.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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@ -74,6 +74,11 @@ struct mlx5_device_context {
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void *context;
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void *context;
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};
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};
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enum {
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MLX5_ATOMIC_REQ_MODE_BE = 0x0,
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MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
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};
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static struct mlx5_profile profile[] = {
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static struct mlx5_profile profile[] = {
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[0] = {
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[0] = {
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.mask = 0,
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.mask = 0,
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@ -383,7 +388,7 @@ int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
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return err;
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return err;
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}
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}
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static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
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static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
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{
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{
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u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
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u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
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int err;
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int err;
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@ -391,6 +396,7 @@ static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
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memset(out, 0, sizeof(out));
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memset(out, 0, sizeof(out));
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MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
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MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
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MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
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err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
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err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
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if (err)
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if (err)
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return err;
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return err;
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@ -400,6 +406,46 @@ static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
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return err;
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return err;
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}
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}
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static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
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{
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void *set_ctx;
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void *set_hca_cap;
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int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
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int req_endianness;
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int err;
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if (MLX5_CAP_GEN(dev, atomic)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
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HCA_CAP_OPMOD_GET_CUR);
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if (err)
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return err;
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} else {
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return 0;
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}
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req_endianness =
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MLX5_CAP_ATOMIC(dev,
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supported_atomic_req_8B_endianess_mode_1);
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if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
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return 0;
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set_ctx = kzalloc(set_sz, GFP_KERNEL);
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if (!set_ctx)
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return -ENOMEM;
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set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
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/* Set requestor to host endianness */
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MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
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MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
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err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
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kfree(set_ctx);
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return err;
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}
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static int handle_hca_cap(struct mlx5_core_dev *dev)
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static int handle_hca_cap(struct mlx5_core_dev *dev)
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{
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{
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void *set_ctx = NULL;
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void *set_ctx = NULL;
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@ -441,7 +487,8 @@ static int handle_hca_cap(struct mlx5_core_dev *dev)
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MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
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MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
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err = set_caps(dev, set_ctx, set_sz);
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err = set_caps(dev, set_ctx, set_sz,
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MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
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query_ex:
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query_ex:
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kfree(set_ctx);
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kfree(set_ctx);
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@ -974,6 +1021,12 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
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goto reclaim_boot_pages;
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goto reclaim_boot_pages;
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}
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}
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err = handle_hca_cap_atomic(dev);
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if (err) {
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dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
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goto reclaim_boot_pages;
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}
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err = mlx5_satisfy_startup_pages(dev, 0);
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err = mlx5_satisfy_startup_pages(dev, 0);
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if (err) {
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if (err) {
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dev_err(&pdev->dev, "failed to allocate init pages\n");
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dev_err(&pdev->dev, "failed to allocate init pages\n");
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@ -66,6 +66,11 @@ enum {
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MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
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MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
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};
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};
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enum {
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MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
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MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
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};
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enum {
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enum {
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MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
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MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
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MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
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MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
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@ -527,21 +532,24 @@ enum {
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struct mlx5_ifc_atomic_caps_bits {
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struct mlx5_ifc_atomic_caps_bits {
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u8 reserved_0[0x40];
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u8 reserved_0[0x40];
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u8 atomic_req_endianness[0x1];
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u8 atomic_req_8B_endianess_mode[0x2];
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u8 reserved_1[0x1f];
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u8 reserved_1[0x4];
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u8 supported_atomic_req_8B_endianess_mode_1[0x1];
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u8 reserved_2[0x20];
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u8 reserved_2[0x19];
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u8 reserved_3[0x10];
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u8 reserved_3[0x20];
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u8 atomic_operations[0x10];
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u8 reserved_4[0x10];
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u8 reserved_4[0x10];
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u8 atomic_size_qp[0x10];
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u8 atomic_operations[0x10];
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u8 reserved_5[0x10];
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u8 reserved_5[0x10];
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u8 atomic_size_qp[0x10];
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u8 reserved_6[0x10];
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u8 atomic_size_dc[0x10];
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u8 atomic_size_dc[0x10];
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u8 reserved_6[0x720];
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u8 reserved_7[0x720];
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};
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};
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struct mlx5_ifc_odp_cap_bits {
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struct mlx5_ifc_odp_cap_bits {
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