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drm/exynos: mixer: remove buffer count handling in vp_video_buffer() 

The video processor (VP) supports four formats: NV12, NV21 and its
tiled variants. All these formats are bi-planar, so the buffer
count in vp_video_buffer() is always 2.

Also properly exit if we're called with an invalid (non-VP) pixelformat.

Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
Tobias Jakobi 2015-04-27 23:10:15 +02:00 committed by Inki Dae
parent 5d878bdb51
commit fac8a5b25f
1 changed files with 2 additions and 15 deletions
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17
drivers/gpu/drm/exynos/exynos_mixer.c
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@ -382,7 +382,6 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
struct mixer_resources *res = &ctx->mixer_res;
unsigned long flags;
struct exynos_drm_plane *plane;
unsigned int buf_num = 1;
dma_addr_t luma_addr[2], chroma_addr[2];
bool tiled_mode = false;
bool crcb_mode = false;
@ -393,27 +392,15 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
switch (plane->pixel_format) {
case DRM_FORMAT_NV12:
crcb_mode = false;
buf_num = 2;
break;
/* TODO: single buffer format NV12, NV21 */
default:
/* ignore pixel format at disable time */
if (!plane->dma_addr[0])
break;
DRM_ERROR("pixel format for vp is wrong [%d].\n",
plane->pixel_format);
return;
}
if (buf_num == 2) {
luma_addr[0] = plane->dma_addr[0];
chroma_addr[0] = plane->dma_addr[1];
} else {
luma_addr[0] = plane->dma_addr[0];
chroma_addr[0] = plane->dma_addr[0]
+ (plane->pitch * plane->fb_height);
}
luma_addr[0] = plane->dma_addr[0];
chroma_addr[0] = plane->dma_addr[1];
if (plane->scan_flag & DRM_MODE_FLAG_INTERLACE) {
ctx->interlace = true;