crypto: caam - Dynamic allocation of addresses for various memory blocks in CAAM.
CAAM's memory is broken into following address blocks: Block Included Registers 0 General Registers 1-4 Job ring registers 6 RTIC registers 7 QI registers 8 DECO and CCB Size of the above stated blocks varies in various platforms. The block size can be 4K or 64K. The block size can be dynamically determined by reading CTPR register in CAAM. This patch initializes the block addresses dynamically based on the value read from this register. Signed-off-by: Ruchika Gupta <r66431@freescale.com> Signed-off-by: Nitesh Narayan Lal <b44382@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Nitesh Narayan Lal
Herbert Xu
parent
ea2d9fc1af
commit
fb4562b208
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@ -1,5 +1,4 @@
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/*
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* CAAM control-plane driver backend
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/* * CAAM control-plane driver backend
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* Controller-level driver, kernel property detection, initialization
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*
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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@ -81,38 +80,37 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
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u32 *status)
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{
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struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
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struct caam_full __iomem *topregs;
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struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
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struct caam_deco __iomem *deco = ctrlpriv->deco;
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unsigned int timeout = 100000;
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u32 deco_dbg_reg, flags;
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int i;
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/* Set the bit to request direct access to DECO0 */
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topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
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if (ctrlpriv->virt_en == 1) {
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setbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
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setbits32(&ctrl->deco_rsr, DECORSR_JR0);
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while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) &&
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while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
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--timeout)
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cpu_relax();
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timeout = 100000;
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}
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setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
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setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
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while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) &&
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while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
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--timeout)
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cpu_relax();
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if (!timeout) {
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dev_err(ctrldev, "failed to acquire DECO 0\n");
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clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
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clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
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return -ENODEV;
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}
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for (i = 0; i < desc_len(desc); i++)
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wr_reg32(&topregs->deco.descbuf[i], *(desc + i));
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wr_reg32(&deco->descbuf[i], *(desc + i));
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flags = DECO_JQCR_WHL;
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/*
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@ -123,11 +121,11 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
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flags |= DECO_JQCR_FOUR;
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/* Instruct the DECO to execute it */
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wr_reg32(&topregs->deco.jr_ctl_hi, flags);
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wr_reg32(&deco->jr_ctl_hi, flags);
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timeout = 10000000;
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do {
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deco_dbg_reg = rd_reg32(&topregs->deco.desc_dbg);
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deco_dbg_reg = rd_reg32(&deco->desc_dbg);
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/*
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* If an error occured in the descriptor, then
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* the DECO status field will be set to 0x0D
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@ -138,14 +136,14 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
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cpu_relax();
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} while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
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*status = rd_reg32(&topregs->deco.op_status_hi) &
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*status = rd_reg32(&deco->op_status_hi) &
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DECO_OP_STATUS_HI_ERR_MASK;
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if (ctrlpriv->virt_en == 1)
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clrbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
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clrbits32(&ctrl->deco_rsr, DECORSR_JR0);
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/* Mark the DECO as free */
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clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
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clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
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if (!timeout)
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return -EAGAIN;
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@ -176,13 +174,13 @@ static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
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int gen_sk)
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{
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struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
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struct caam_full __iomem *topregs;
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struct caam_ctrl __iomem *ctrl;
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struct rng4tst __iomem *r4tst;
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u32 *desc, status, rdsta_val;
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int ret = 0, sh_idx;
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topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
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r4tst = &topregs->ctrl.r4tst[0];
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ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
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r4tst = &ctrl->r4tst[0];
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desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
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if (!desc)
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@ -212,12 +210,11 @@ static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
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* CAAM eras), then try again.
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*/
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rdsta_val =
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rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IFMASK;
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rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
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if (status || !(rdsta_val & (1 << sh_idx)))
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ret = -EAGAIN;
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if (ret)
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break;
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dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
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/* Clear the contents before recreating the descriptor */
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memset(desc, 0x00, CAAM_CMD_SZ * 7);
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@ -285,12 +282,12 @@ static int caam_remove(struct platform_device *pdev)
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{
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struct device *ctrldev;
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struct caam_drv_private *ctrlpriv;
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struct caam_full __iomem *topregs;
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struct caam_ctrl __iomem *ctrl;
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int ring, ret = 0;
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ctrldev = &pdev->dev;
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ctrlpriv = dev_get_drvdata(ctrldev);
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topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
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ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
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/* Remove platform devices for JobRs */
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for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
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@ -308,7 +305,7 @@ static int caam_remove(struct platform_device *pdev)
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#endif
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/* Unmap controller region */
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iounmap(&topregs->ctrl);
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iounmap(&ctrl);
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return ret;
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}
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@ -323,12 +320,12 @@ static void kick_trng(struct platform_device *pdev, int ent_delay)
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{
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struct device *ctrldev = &pdev->dev;
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struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
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struct caam_full __iomem *topregs;
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struct caam_ctrl __iomem *ctrl;
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struct rng4tst __iomem *r4tst;
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u32 val;
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topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
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r4tst = &topregs->ctrl.r4tst[0];
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ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
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r4tst = &ctrl->r4tst[0];
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/* put RNG4 into program mode */
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setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
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@ -396,13 +393,14 @@ static int caam_probe(struct platform_device *pdev)
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struct device *dev;
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struct device_node *nprop, *np;
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struct caam_ctrl __iomem *ctrl;
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struct caam_full __iomem *topregs;
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struct caam_drv_private *ctrlpriv;
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#ifdef CONFIG_DEBUG_FS
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struct caam_perfmon *perfmon;
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#endif
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u32 scfgr, comp_params;
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u32 cha_vid_ls;
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int pg_size;
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int BLOCK_OFFSET = 0;
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ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private),
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GFP_KERNEL);
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@ -421,10 +419,27 @@ static int caam_probe(struct platform_device *pdev)
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dev_err(dev, "caam: of_iomap() failed\n");
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return -ENOMEM;
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}
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ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
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/* Finding the page size for using the CTPR_MS register */
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comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
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pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
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/* topregs used to derive pointers to CAAM sub-blocks only */
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topregs = (struct caam_full __iomem *)ctrl;
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/* Allocating the BLOCK_OFFSET based on the supported page size on
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* the platform
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*/
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if (pg_size == 0)
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BLOCK_OFFSET = PG_SIZE_4K;
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else
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BLOCK_OFFSET = PG_SIZE_64K;
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ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
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ctrlpriv->assure = (struct caam_assurance __force *)
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((uint8_t *)ctrl +
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BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
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);
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ctrlpriv->deco = (struct caam_deco __force *)
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((uint8_t *)ctrl +
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BLOCK_OFFSET * DECO_BLOCK_NUMBER
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);
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/* Get the IRQ of the controller (for security violations only) */
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ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
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@ -433,15 +448,14 @@ static int caam_probe(struct platform_device *pdev)
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* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
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* long pointers in master configuration register
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*/
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setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
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setbits32(&ctrl->mcr, MCFGR_WDENABLE |
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(sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
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/*
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* Read the Compile Time paramters and SCFGR to determine
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* if Virtualization is enabled for this platform
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*/
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comp_params = rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms);
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scfgr = rd_reg32(&topregs->ctrl.scfgr);
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scfgr = rd_reg32(&ctrl->scfgr);
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ctrlpriv->virt_en = 0;
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if (comp_params & CTPR_MS_VIRT_EN_INCL) {
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@ -459,7 +473,7 @@ static int caam_probe(struct platform_device *pdev)
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}
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if (ctrlpriv->virt_en == 1)
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setbits32(&topregs->ctrl.jrstart, JRSTART_JR0_START |
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setbits32(&ctrl->jrstart, JRSTART_JR0_START |
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JRSTART_JR1_START | JRSTART_JR2_START |
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JRSTART_JR3_START);
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@ -486,7 +500,7 @@ static int caam_probe(struct platform_device *pdev)
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sizeof(struct platform_device *) * rspec,
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GFP_KERNEL);
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if (ctrlpriv->jrpdev == NULL) {
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iounmap(&topregs->ctrl);
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iounmap(&ctrl);
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return -ENOMEM;
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}
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@ -502,18 +516,26 @@ static int caam_probe(struct platform_device *pdev)
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ring);
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continue;
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}
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ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
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((uint8_t *)ctrl +
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(ring + JR_BLOCK_NUMBER) *
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BLOCK_OFFSET
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);
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ctrlpriv->total_jobrs++;
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ring++;
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}
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}
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/* Check to see if QI present. If so, enable */
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ctrlpriv->qi_present =
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!!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) &
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!!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
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CTPR_MS_QI_MASK);
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if (ctrlpriv->qi_present) {
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ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
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ctrlpriv->qi = (struct caam_queue_if __force *)
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((uint8_t *)ctrl +
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BLOCK_OFFSET * QI_BLOCK_NUMBER
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);
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/* This is all that's required to physically enable QI */
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wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN);
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wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
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}
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/* If no QI and no rings specified, quit and go home */
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@ -523,7 +545,7 @@ static int caam_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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cha_vid_ls = rd_reg32(&topregs->ctrl.perfmon.cha_id_ls);
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cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
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/*
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* If SEC has RNG version >= 4 and RNG state handle has not been
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@ -531,7 +553,7 @@ static int caam_probe(struct platform_device *pdev)
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*/
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if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
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ctrlpriv->rng4_sh_init =
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rd_reg32(&topregs->ctrl.r4tst[0].rdsta);
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rd_reg32(&ctrl->r4tst[0].rdsta);
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/*
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* If the secure keys (TDKEK, JDKEK, TDSK), were already
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* generated, signal this to the function that is instantiating
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@ -542,7 +564,7 @@ static int caam_probe(struct platform_device *pdev)
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ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
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do {
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int inst_handles =
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rd_reg32(&topregs->ctrl.r4tst[0].rdsta) &
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rd_reg32(&ctrl->r4tst[0].rdsta) &
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RDSTA_IFMASK;
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/*
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* If either SH were instantiated by somebody else
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@ -587,13 +609,13 @@ static int caam_probe(struct platform_device *pdev)
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ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
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/* Enable RDB bit so that RNG works faster */
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setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
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setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
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}
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/* NOTE: RTIC detection ought to go here, around Si time */
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caam_id = (u64)rd_reg32(&topregs->ctrl.perfmon.caam_id_ms) << 32 |
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(u64)rd_reg32(&topregs->ctrl.perfmon.caam_id_ls);
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caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
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(u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
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/* Report "alive" for developer to see */
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dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
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@ -70,10 +70,11 @@ struct caam_drv_private {
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struct platform_device *pdev;
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/* Physical-presence section */
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struct caam_ctrl *ctrl; /* controller region */
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struct caam_deco **deco; /* DECO/CCB views */
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struct caam_assurance *ac;
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struct caam_queue_if *qi; /* QI control region */
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struct caam_ctrl __iomem *ctrl; /* controller region */
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struct caam_deco __iomem *deco; /* DECO/CCB views */
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struct caam_assurance __iomem *assure;
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struct caam_queue_if __iomem *qi; /* QI control region */
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struct caam_job_ring __iomem *jr[4]; /* JobR's register space */
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/*
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* Detected geometry block. Filled in from device tree if powerpc,
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@ -194,6 +194,8 @@ struct caam_perfmon {
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#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
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#define CTPR_MS_VIRT_EN_INCL 0x00000001
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#define CTPR_MS_VIRT_EN_POR 0x00000002
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#define CTPR_MS_PG_SZ_MASK 0x10
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#define CTPR_MS_PG_SZ_SHIFT 4
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u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
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u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
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u64 rsvd1[2];
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@ -769,34 +771,10 @@ struct caam_deco {
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#define DECO_JQCR_WHL 0x20000000
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#define DECO_JQCR_FOUR 0x10000000
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/*
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* Current top-level view of memory map is:
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*
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* 0x0000 - 0x0fff - CAAM Top-Level Control
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* 0x1000 - 0x1fff - Job Ring 0
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* 0x2000 - 0x2fff - Job Ring 1
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* 0x3000 - 0x3fff - Job Ring 2
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* 0x4000 - 0x4fff - Job Ring 3
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* 0x5000 - 0x5fff - (unused)
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* 0x6000 - 0x6fff - Assurance Controller
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* 0x7000 - 0x7fff - Queue Interface
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* 0x8000 - 0x8fff - DECO-CCB 0
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* 0x9000 - 0x9fff - DECO-CCB 1
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* 0xa000 - 0xafff - DECO-CCB 2
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* 0xb000 - 0xbfff - DECO-CCB 3
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* 0xc000 - 0xcfff - DECO-CCB 4
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*
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* caam_full describes the full register view of CAAM if useful,
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* although many configurations may choose to implement parts of
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* the register map separately, in differing privilege regions
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*/
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struct caam_full {
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struct caam_ctrl __iomem ctrl;
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struct caam_job_ring jr[4];
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u64 rsvd[512];
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struct caam_assurance assure;
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struct caam_queue_if qi;
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struct caam_deco deco;
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};
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#define JR_BLOCK_NUMBER 1
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#define ASSURE_BLOCK_NUMBER 6
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#define QI_BLOCK_NUMBER 7
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#define DECO_BLOCK_NUMBER 8
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#define PG_SIZE_4K 0x1000
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#define PG_SIZE_64K 0x10000
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#endif /* REGS_H */
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