pinctrl: sh-pfc: r8a7796: Add SCIF pins, groups and functions
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796
SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Takeshi Kihara
Geert Uytterhoeven
parent
f9aece7344
commit
fc43d8b217
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@ -1486,10 +1486,310 @@ static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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};
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/* - SCIF0 ------------------------------------------------------------------ */
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static const unsigned int scif0_data_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
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};
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static const unsigned int scif0_data_mux[] = {
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RX0_MARK, TX0_MARK,
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};
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static const unsigned int scif0_clk_pins[] = {
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/* SCK */
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RCAR_GP_PIN(5, 0),
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};
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static const unsigned int scif0_clk_mux[] = {
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SCK0_MARK,
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};
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static const unsigned int scif0_ctrl_pins[] = {
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/* RTS, CTS */
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RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
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};
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static const unsigned int scif0_ctrl_mux[] = {
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RTS0_N_TANS_MARK, CTS0_N_MARK,
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};
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/* - SCIF1 ------------------------------------------------------------------ */
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static const unsigned int scif1_data_a_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
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};
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static const unsigned int scif1_data_a_mux[] = {
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RX1_A_MARK, TX1_A_MARK,
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};
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static const unsigned int scif1_clk_pins[] = {
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/* SCK */
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RCAR_GP_PIN(6, 21),
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};
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static const unsigned int scif1_clk_mux[] = {
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SCK1_MARK,
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};
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static const unsigned int scif1_ctrl_pins[] = {
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/* RTS, CTS */
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RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
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};
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static const unsigned int scif1_ctrl_mux[] = {
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RTS1_N_TANS_MARK, CTS1_N_MARK,
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};
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static const unsigned int scif1_data_b_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
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};
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static const unsigned int scif1_data_b_mux[] = {
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RX1_B_MARK, TX1_B_MARK,
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};
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/* - SCIF2 ------------------------------------------------------------------ */
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static const unsigned int scif2_data_a_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
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};
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static const unsigned int scif2_data_a_mux[] = {
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RX2_A_MARK, TX2_A_MARK,
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};
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static const unsigned int scif2_clk_pins[] = {
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/* SCK */
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RCAR_GP_PIN(5, 9),
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};
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static const unsigned int scif2_clk_mux[] = {
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SCK2_MARK,
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};
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static const unsigned int scif2_data_b_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
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};
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static const unsigned int scif2_data_b_mux[] = {
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RX2_B_MARK, TX2_B_MARK,
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};
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/* - SCIF3 ------------------------------------------------------------------ */
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static const unsigned int scif3_data_a_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
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};
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static const unsigned int scif3_data_a_mux[] = {
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RX3_A_MARK, TX3_A_MARK,
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};
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static const unsigned int scif3_clk_pins[] = {
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/* SCK */
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RCAR_GP_PIN(1, 22),
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};
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static const unsigned int scif3_clk_mux[] = {
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SCK3_MARK,
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};
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static const unsigned int scif3_ctrl_pins[] = {
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/* RTS, CTS */
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RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
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};
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static const unsigned int scif3_ctrl_mux[] = {
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RTS3_N_TANS_MARK, CTS3_N_MARK,
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};
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static const unsigned int scif3_data_b_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
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};
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static const unsigned int scif3_data_b_mux[] = {
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RX3_B_MARK, TX3_B_MARK,
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};
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/* - SCIF4 ------------------------------------------------------------------ */
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static const unsigned int scif4_data_a_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
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};
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static const unsigned int scif4_data_a_mux[] = {
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RX4_A_MARK, TX4_A_MARK,
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};
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static const unsigned int scif4_clk_a_pins[] = {
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/* SCK */
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RCAR_GP_PIN(2, 10),
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};
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static const unsigned int scif4_clk_a_mux[] = {
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SCK4_A_MARK,
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};
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static const unsigned int scif4_ctrl_a_pins[] = {
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/* RTS, CTS */
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RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
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};
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static const unsigned int scif4_ctrl_a_mux[] = {
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RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
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};
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static const unsigned int scif4_data_b_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
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};
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static const unsigned int scif4_data_b_mux[] = {
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RX4_B_MARK, TX4_B_MARK,
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};
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static const unsigned int scif4_clk_b_pins[] = {
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/* SCK */
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RCAR_GP_PIN(1, 5),
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};
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static const unsigned int scif4_clk_b_mux[] = {
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SCK4_B_MARK,
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};
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static const unsigned int scif4_ctrl_b_pins[] = {
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/* RTS, CTS */
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RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
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};
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static const unsigned int scif4_ctrl_b_mux[] = {
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RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
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};
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static const unsigned int scif4_data_c_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
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};
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static const unsigned int scif4_data_c_mux[] = {
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RX4_C_MARK, TX4_C_MARK,
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};
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static const unsigned int scif4_clk_c_pins[] = {
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/* SCK */
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RCAR_GP_PIN(0, 8),
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};
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static const unsigned int scif4_clk_c_mux[] = {
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SCK4_C_MARK,
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};
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static const unsigned int scif4_ctrl_c_pins[] = {
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/* RTS, CTS */
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RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
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};
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static const unsigned int scif4_ctrl_c_mux[] = {
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RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
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};
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/* - SCIF5 ------------------------------------------------------------------ */
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static const unsigned int scif5_data_a_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
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};
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static const unsigned int scif5_data_a_mux[] = {
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RX5_A_MARK, TX5_A_MARK,
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};
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static const unsigned int scif5_clk_a_pins[] = {
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/* SCK */
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RCAR_GP_PIN(6, 21),
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};
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static const unsigned int scif5_clk_a_mux[] = {
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SCK5_A_MARK,
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};
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static const unsigned int scif5_data_b_pins[] = {
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/* RX, TX */
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RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
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};
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static const unsigned int scif5_data_b_mux[] = {
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RX5_B_MARK, TX5_B_MARK,
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};
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static const unsigned int scif5_clk_b_pins[] = {
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/* SCK */
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RCAR_GP_PIN(5, 0),
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};
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static const unsigned int scif5_clk_b_mux[] = {
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SCK5_B_MARK,
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};
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/* - SCIF Clock ------------------------------------------------------------- */
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static const unsigned int scif_clk_a_pins[] = {
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/* SCIF_CLK */
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RCAR_GP_PIN(6, 23),
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};
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static const unsigned int scif_clk_a_mux[] = {
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SCIF_CLK_A_MARK,
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};
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static const unsigned int scif_clk_b_pins[] = {
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/* SCIF_CLK */
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RCAR_GP_PIN(5, 9),
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};
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static const unsigned int scif_clk_b_mux[] = {
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SCIF_CLK_B_MARK,
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};
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static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scif0_data),
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SH_PFC_PIN_GROUP(scif0_clk),
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SH_PFC_PIN_GROUP(scif0_ctrl),
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SH_PFC_PIN_GROUP(scif1_data_a),
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SH_PFC_PIN_GROUP(scif1_clk),
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SH_PFC_PIN_GROUP(scif1_ctrl),
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SH_PFC_PIN_GROUP(scif1_data_b),
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SH_PFC_PIN_GROUP(scif2_data_a),
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SH_PFC_PIN_GROUP(scif2_clk),
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SH_PFC_PIN_GROUP(scif2_data_b),
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SH_PFC_PIN_GROUP(scif3_data_a),
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SH_PFC_PIN_GROUP(scif3_clk),
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SH_PFC_PIN_GROUP(scif3_ctrl),
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SH_PFC_PIN_GROUP(scif3_data_b),
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SH_PFC_PIN_GROUP(scif4_data_a),
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SH_PFC_PIN_GROUP(scif4_clk_a),
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SH_PFC_PIN_GROUP(scif4_ctrl_a),
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SH_PFC_PIN_GROUP(scif4_data_b),
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SH_PFC_PIN_GROUP(scif4_clk_b),
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SH_PFC_PIN_GROUP(scif4_ctrl_b),
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SH_PFC_PIN_GROUP(scif4_data_c),
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SH_PFC_PIN_GROUP(scif4_clk_c),
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SH_PFC_PIN_GROUP(scif4_ctrl_c),
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SH_PFC_PIN_GROUP(scif5_data_a),
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SH_PFC_PIN_GROUP(scif5_clk_a),
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SH_PFC_PIN_GROUP(scif5_data_b),
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SH_PFC_PIN_GROUP(scif5_clk_b),
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SH_PFC_PIN_GROUP(scif_clk_a),
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SH_PFC_PIN_GROUP(scif_clk_b),
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};
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static const char * const scif0_groups[] = {
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"scif0_data",
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"scif0_clk",
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"scif0_ctrl",
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};
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static const char * const scif1_groups[] = {
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"scif1_data_a",
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"scif1_clk",
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"scif1_ctrl",
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"scif1_data_b",
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};
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static const char * const scif2_groups[] = {
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"scif2_data_a",
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"scif2_clk",
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"scif2_data_b",
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};
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static const char * const scif3_groups[] = {
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"scif3_data_a",
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"scif3_clk",
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"scif3_ctrl",
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"scif3_data_b",
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};
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static const char * const scif4_groups[] = {
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"scif4_data_a",
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"scif4_clk_a",
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"scif4_ctrl_a",
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"scif4_data_b",
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"scif4_clk_b",
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"scif4_ctrl_b",
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"scif4_data_c",
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"scif4_clk_c",
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"scif4_ctrl_c",
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};
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static const char * const scif5_groups[] = {
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"scif5_data_a",
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"scif5_clk_a",
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"scif5_data_b",
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"scif5_clk_b",
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};
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static const char * const scif_clk_groups[] = {
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"scif_clk_a",
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"scif_clk_b",
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};
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(scif0),
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SH_PFC_FUNCTION(scif1),
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SH_PFC_FUNCTION(scif2),
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SH_PFC_FUNCTION(scif3),
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SH_PFC_FUNCTION(scif4),
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SH_PFC_FUNCTION(scif5),
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SH_PFC_FUNCTION(scif_clk),
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};
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static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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