mtd: rawnand: fsmc: Fix all coding style issues reported by checkpatch
checkpatch reports a bunch of coding style issues. Let's fix them all in one step. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Boris Brezillon
Miquel Raynal
parent
bb6963449f
commit
fc43f45ed5
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@ -38,15 +38,14 @@
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/* fsmc controller registers for NOR flash */
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#define CTRL 0x0
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/* ctrl register definitions */
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#define BANK_ENABLE (1 << 0)
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#define MUXED (1 << 1)
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#define BANK_ENABLE BIT(0)
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#define MUXED BIT(1)
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#define NOR_DEV (2 << 2)
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#define WIDTH_8 (0 << 4)
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#define WIDTH_16 (1 << 4)
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#define RSTPWRDWN (1 << 6)
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#define WPROT (1 << 7)
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#define WRT_ENABLE (1 << 12)
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#define WAIT_ENB (1 << 13)
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#define WIDTH_16 BIT(4)
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#define RSTPWRDWN BIT(6)
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#define WPROT BIT(7)
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#define WRT_ENABLE BIT(12)
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#define WAIT_ENB BIT(13)
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#define CTRL_TIM 0x4
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/* ctrl_tim register definitions */
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@ -54,43 +53,35 @@
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#define FSMC_NOR_BANK_SZ 0x8
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#define FSMC_NOR_REG_SIZE 0x40
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#define FSMC_NOR_REG(base, bank, reg) (base + \
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FSMC_NOR_BANK_SZ * (bank) + \
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reg)
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#define FSMC_NOR_REG(base, bank, reg) ((base) + \
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(FSMC_NOR_BANK_SZ * (bank)) + \
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(reg))
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/* fsmc controller registers for NAND flash */
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#define FSMC_PC 0x00
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1)
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#define FSMC_RESET BIT(0)
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#define FSMC_WAITON BIT(1)
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#define FSMC_ENABLE BIT(2)
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#define FSMC_DEVTYPE_NAND BIT(3)
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#define FSMC_DEVWID_16 BIT(4)
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#define FSMC_ECCEN BIT(6)
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#define FSMC_ECCPLEN_256 BIT(7)
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#define FSMC_TCLR_SHIFT (9)
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#define FSMC_TCLR_MASK (0xF)
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#define FSMC_TAR_1 (1)
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#define FSMC_TAR_SHIFT (13)
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#define FSMC_TAR_MASK (0xF)
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#define STS 0x04
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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#define FSMC_CODE_RDY BIT(15)
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#define COMM 0x08
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/* comm register definitions */
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#define FSMC_TSET_0 0
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#define FSMC_TSET_SHIFT 0
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#define FSMC_TSET_MASK 0xFF
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#define FSMC_TWAIT_6 6
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#define FSMC_TWAIT_SHIFT 8
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#define FSMC_TWAIT_MASK 0xFF
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#define FSMC_THOLD_4 4
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#define FSMC_THOLD_SHIFT 16
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#define FSMC_THOLD_MASK 0xFF
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#define FSMC_THIZ_1 1
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#define FSMC_THIZ_SHIFT 24
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#define FSMC_THIZ_MASK 0xFF
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#define ATTRIB 0x0C
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@ -103,12 +94,12 @@
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#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
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struct fsmc_nand_timings {
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uint8_t tclr;
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uint8_t tar;
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uint8_t thiz;
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uint8_t thold;
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uint8_t twait;
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uint8_t tset;
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u8 tclr;
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u8 tar;
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u8 thiz;
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u8 thold;
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u8 twait;
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u8 tset;
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};
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enum access_mode {
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@ -262,8 +253,8 @@ static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
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static void fsmc_nand_setup(struct fsmc_nand_data *host,
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struct fsmc_nand_timings *tims)
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{
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uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
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uint32_t tclr, tar, thiz, thold, twait, tset;
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u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
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u32 tclr, tar, thiz, thold, twait, tset;
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tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
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tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
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@ -273,13 +264,9 @@ static void fsmc_nand_setup(struct fsmc_nand_data *host,
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tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
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if (host->nand.options & NAND_BUSWIDTH_16)
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writel_relaxed(value | FSMC_DEVWID_16,
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host->regs_va + FSMC_PC);
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else
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writel_relaxed(value | FSMC_DEVWID_8, host->regs_va + FSMC_PC);
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value |= FSMC_DEVWID_16;
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writel_relaxed(readl(host->regs_va + FSMC_PC) | tclr | tar,
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host->regs_va + FSMC_PC);
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writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
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writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
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writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
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}
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@ -290,7 +277,7 @@ static int fsmc_calc_timings(struct fsmc_nand_data *host,
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{
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unsigned long hclk = clk_get_rate(host->clk);
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unsigned long hclkn = NSEC_PER_SEC / hclk;
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uint32_t thiz, thold, twait, tset;
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u32 thiz, thold, twait, tset;
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if (sdrt->tRC_min < 30000)
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return -EOPNOTSUPP;
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@ -384,18 +371,18 @@ static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
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* FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
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* max of 8-bits)
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*/
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static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const uint8_t *data,
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uint8_t *ecc)
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static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
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u8 *ecc)
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{
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struct fsmc_nand_data *host = nand_to_fsmc(chip);
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uint32_t ecc_tmp;
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u32 ecc_tmp;
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unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
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do {
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if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
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break;
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else
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cond_resched();
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cond_resched();
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} while (!time_after_eq(jiffies, deadline));
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if (time_after_eq(jiffies, deadline)) {
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@ -404,25 +391,25 @@ static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const uint8_t *data,
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}
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ecc_tmp = readl_relaxed(host->regs_va + ECC1);
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ecc[0] = (uint8_t) (ecc_tmp >> 0);
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ecc[1] = (uint8_t) (ecc_tmp >> 8);
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ecc[2] = (uint8_t) (ecc_tmp >> 16);
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ecc[3] = (uint8_t) (ecc_tmp >> 24);
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ecc[0] = ecc_tmp;
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ecc[1] = ecc_tmp >> 8;
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ecc[2] = ecc_tmp >> 16;
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ecc[3] = ecc_tmp >> 24;
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ecc_tmp = readl_relaxed(host->regs_va + ECC2);
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ecc[4] = (uint8_t) (ecc_tmp >> 0);
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ecc[5] = (uint8_t) (ecc_tmp >> 8);
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ecc[6] = (uint8_t) (ecc_tmp >> 16);
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ecc[7] = (uint8_t) (ecc_tmp >> 24);
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ecc[4] = ecc_tmp;
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ecc[5] = ecc_tmp >> 8;
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ecc[6] = ecc_tmp >> 16;
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ecc[7] = ecc_tmp >> 24;
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ecc_tmp = readl_relaxed(host->regs_va + ECC3);
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ecc[8] = (uint8_t) (ecc_tmp >> 0);
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ecc[9] = (uint8_t) (ecc_tmp >> 8);
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ecc[10] = (uint8_t) (ecc_tmp >> 16);
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ecc[11] = (uint8_t) (ecc_tmp >> 24);
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ecc[8] = ecc_tmp;
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ecc[9] = ecc_tmp >> 8;
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ecc[10] = ecc_tmp >> 16;
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ecc[11] = ecc_tmp >> 24;
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ecc_tmp = readl_relaxed(host->regs_va + STS);
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ecc[12] = (uint8_t) (ecc_tmp >> 16);
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ecc[12] = ecc_tmp >> 16;
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return 0;
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}
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@ -432,22 +419,22 @@ static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const uint8_t *data,
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* FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
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* max of 1-bit)
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*/
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static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const uint8_t *data,
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uint8_t *ecc)
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static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
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u8 *ecc)
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{
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struct fsmc_nand_data *host = nand_to_fsmc(chip);
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uint32_t ecc_tmp;
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u32 ecc_tmp;
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ecc_tmp = readl_relaxed(host->regs_va + ECC1);
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ecc[0] = (uint8_t) (ecc_tmp >> 0);
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ecc[1] = (uint8_t) (ecc_tmp >> 8);
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ecc[2] = (uint8_t) (ecc_tmp >> 16);
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ecc[0] = ecc_tmp;
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ecc[1] = ecc_tmp >> 8;
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ecc[2] = ecc_tmp >> 16;
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return 0;
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}
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/* Count the number of 0's in buff upto a max of max_bits */
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static int count_written_bits(uint8_t *buff, int size, int max_bits)
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static int count_written_bits(u8 *buff, int size, int max_bits)
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{
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int k, written_bits = 0;
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@ -468,7 +455,7 @@ static void dma_complete(void *param)
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}
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static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
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enum dma_data_direction direction)
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enum dma_data_direction direction)
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{
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struct dma_chan *chan;
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struct dma_device *dma_dev;
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@ -519,7 +506,7 @@ static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
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time_left =
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wait_for_completion_timeout(&host->dma_access_complete,
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msecs_to_jiffies(3000));
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msecs_to_jiffies(3000));
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if (time_left == 0) {
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dmaengine_terminate_all(chan);
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dev_err(host->dev, "wait_for_completion_timeout\n");
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@ -541,14 +528,15 @@ static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void fsmc_write_buf(struct fsmc_nand_data *host, const uint8_t *buf,
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static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
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int len)
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{
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int i;
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if (IS_ALIGNED((uintptr_t)buf, sizeof(uint32_t)) &&
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IS_ALIGNED(len, sizeof(uint32_t))) {
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uint32_t *p = (uint32_t *)buf;
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if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
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IS_ALIGNED(len, sizeof(u32))) {
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u32 *p = (u32 *)buf;
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len = len >> 2;
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for (i = 0; i < len; i++)
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writel_relaxed(p[i], host->data_va);
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@ -564,13 +552,14 @@ static void fsmc_write_buf(struct fsmc_nand_data *host, const uint8_t *buf,
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void fsmc_read_buf(struct fsmc_nand_data *host, uint8_t *buf, int len)
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static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
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{
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int i;
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if (IS_ALIGNED((uintptr_t)buf, sizeof(uint32_t)) &&
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IS_ALIGNED(len, sizeof(uint32_t))) {
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uint32_t *p = (uint32_t *)buf;
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if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
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IS_ALIGNED(len, sizeof(u32))) {
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u32 *p = (u32 *)buf;
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len = len >> 2;
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for (i = 0; i < len; i++)
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p[i] = readl_relaxed(host->data_va);
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@ -586,7 +575,7 @@ static void fsmc_read_buf(struct fsmc_nand_data *host, uint8_t *buf, int len)
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void fsmc_read_buf_dma(struct fsmc_nand_data *host, uint8_t *buf,
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static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
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int len)
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{
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dma_xfer(host, buf, len, DMA_FROM_DEVICE);
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@ -598,7 +587,7 @@ static void fsmc_read_buf_dma(struct fsmc_nand_data *host, uint8_t *buf,
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const uint8_t *buf,
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static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
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int len)
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{
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dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
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@ -679,7 +668,8 @@ static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
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", force 8-bit" : "");
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if (host->mode == USE_DMA_ACCESS)
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fsmc_write_buf_dma(host, instr->ctx.data.buf.out,
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fsmc_write_buf_dma(host,
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instr->ctx.data.buf.out,
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instr->ctx.data.len);
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else
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fsmc_write_buf(host, instr->ctx.data.buf.out,
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@ -714,24 +704,24 @@ static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
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* After this read, fsmc hardware generates and reports error data bits(up to a
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* max of 8 bits)
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*/
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static int fsmc_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
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static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
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int oob_required, int page)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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int i, j, s, stat, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint8_t *p = buf;
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uint8_t *ecc_calc = chip->ecc.calc_buf;
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uint8_t *ecc_code = chip->ecc.code_buf;
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u8 *p = buf;
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u8 *ecc_calc = chip->ecc.calc_buf;
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u8 *ecc_code = chip->ecc.code_buf;
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int off, len, ret, group = 0;
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/*
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* ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
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* ecc_oob is intentionally taken as u16. In 16bit devices, we
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* end up reading 14 bytes (7 words) from oob. The local array is
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* to maintain word alignment
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*/
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uint16_t ecc_oob[7];
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uint8_t *oob = (uint8_t *)&ecc_oob[0];
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u16 ecc_oob[7];
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u8 *oob = (u8 *)&ecc_oob[0];
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unsigned int max_bitflips = 0;
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for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
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@ -786,15 +776,15 @@ static int fsmc_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
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* @calc_ecc: ecc calculated from read data
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*
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* calc_ecc is a 104 bit information containing maximum of 8 error
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* offset informations of 13 bits each in 512 bytes of read data.
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* offset information of 13 bits each in 512 bytes of read data.
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*/
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static int fsmc_bch8_correct_data(struct nand_chip *chip, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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struct fsmc_nand_data *host = nand_to_fsmc(chip);
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uint32_t err_idx[8];
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uint32_t num_err, i;
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uint32_t ecc1, ecc2, ecc3, ecc4;
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u32 err_idx[8];
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u32 num_err, i;
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u32 ecc1, ecc2, ecc3, ecc4;
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num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
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@ -835,8 +825,8 @@ static int fsmc_bch8_correct_data(struct nand_chip *chip, uint8_t *dat,
|
|||
* |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
|
||||
*
|
||||
* calc_ecc is a 104 bit information containing maximum of 8 error
|
||||
* offset informations of 13 bits each. calc_ecc is copied into a
|
||||
* uint64_t array and error offset indexes are populated in err_idx
|
||||
* offset information of 13 bits each. calc_ecc is copied into a
|
||||
* u64 array and error offset indexes are populated in err_idx
|
||||
* array
|
||||
*/
|
||||
ecc1 = readl_relaxed(host->regs_va + ECC1);
|
||||
|
|
@ -895,11 +885,13 @@ static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
|
|||
nand->options |= NAND_SKIP_BBTSCAN;
|
||||
|
||||
host->dev_timings = devm_kzalloc(&pdev->dev,
|
||||
sizeof(*host->dev_timings), GFP_KERNEL);
|
||||
sizeof(*host->dev_timings),
|
||||
GFP_KERNEL);
|
||||
if (!host->dev_timings)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
|
||||
sizeof(*host->dev_timings));
|
||||
sizeof(*host->dev_timings));
|
||||
if (ret)
|
||||
host->dev_timings = NULL;
|
||||
|
||||
|
|
@ -1061,10 +1053,13 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
|
|||
* AMBA PrimeCell bus. However it is not a PrimeCell.
|
||||
*/
|
||||
for (pid = 0, i = 0; i < 4; i++)
|
||||
pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
|
||||
pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
|
||||
255) << (i * 8);
|
||||
|
||||
host->pid = pid;
|
||||
dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
|
||||
"revision %02x, config %02x\n",
|
||||
|
||||
dev_info(&pdev->dev,
|
||||
"FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
|
||||
AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
|
||||
AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
|
||||
|
||||
|
|
@ -1175,19 +1170,23 @@ static int fsmc_nand_remove(struct platform_device *pdev)
|
|||
static int fsmc_nand_suspend(struct device *dev)
|
||||
{
|
||||
struct fsmc_nand_data *host = dev_get_drvdata(dev);
|
||||
|
||||
if (host)
|
||||
clk_disable_unprepare(host->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsmc_nand_resume(struct device *dev)
|
||||
{
|
||||
struct fsmc_nand_data *host = dev_get_drvdata(dev);
|
||||
|
||||
if (host) {
|
||||
clk_prepare_enable(host->clk);
|
||||
if (host->dev_timings)
|
||||
fsmc_nand_setup(host, host->dev_timings);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue