clk: tegra: Changes for v5.17-rc1
This contains a simple fix for the VDE clock on Tegra114 and some preparation work to support runtime PM and generic power domains. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmG8r9ITHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoTZZD/4sXPJ3KRt+KHi2KzNlw1F1VuzL54cy 8mvxxHnvQzoHAhzciphCbNphn39gQ06nZP9Wmdlj4WmEY7zzpDcKTdM+dQwgoGrM IEqg4B13qNi7gaFpahoN0Ygjp/C6x8R2b18KKrytp4UemLuEH7IPL1utHm7YWzye srUymc20Fs49qbHwOyyyLp7lg9Kpn3oSRSxVSZbpmUK+r465MnXlxgrHtur+UaKF dV7I3UQuNJxLng5E6t8/LgFo2FwPKrYUit8/vhwUiGO1IbfSOlVzKcWn7J1Yfo7y IDRfrYMXu/TYObCzE3qTiMSEhUWz+uhfDonUhFNHXI0qCpx94k0MhjEGhDyZknJG 8alwumFP8NX96N/CC+GWnJhuGf6M32gte6O1Yh9aa6jA4OwsuDXdx8YRu/R3ABYz 7rgfENGarl5UvgcNr8smNc03r8BZrkMl2wkLU6owUI+CY3ToY8R99ncvfuKE7ZFq ATezvxWmjjlcfdSxDjVb7PJvBmLNwPGOv/dTSKXcRcrnAFyqZgnW7zGKXSJdBIbB QYHeo7GpLbZoiJvqUsn7AT85NZyIIPwD5kkRMTg2TlV1To7H/sKzKsVNl2y9j4Nd WHxc2zawuU8a09fz2RQDe7sQTR0Kn9WchYSnITTpunhymqbPa7nc8B56LTuMoKAN 0ywl+4UfbDRvYQ== =aQXh -----END PGP SIGNATURE----- Merge tag 'for-5.17-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nvidia Pull Tegra clk driver updates from Thierry Reding: This contains a simple fix for the VDE clock on Tegra114 and some preparation work to support runtime PM and generic power domains. * tag 'for-5.17-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Support runtime PM and power domain clk: tegra: Make vde a child of pll_p on tegra114
This commit is contained in:
Stephen Boyd
commit
fcfc6ea4a4
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += clk.o
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obj-y += clk-audio-sync.o
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obj-y += clk-device.o
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obj-y += clk-dfll.o
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obj-y += clk-divider.o
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obj-y += clk-periph.o
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@ -0,0 +1,199 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <soc/tegra/common.h>
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#include "clk.h"
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/*
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* This driver manages performance state of the core power domain for the
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* independent PLLs and system clocks. We created a virtual clock device
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* for such clocks, see tegra_clk_dev_register().
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*/
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struct tegra_clk_device {
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struct notifier_block clk_nb;
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struct device *dev;
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struct clk_hw *hw;
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struct mutex lock;
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};
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static int tegra_clock_set_pd_state(struct tegra_clk_device *clk_dev,
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unsigned long rate)
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{
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struct device *dev = clk_dev->dev;
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struct dev_pm_opp *opp;
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unsigned int pstate;
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opp = dev_pm_opp_find_freq_ceil(dev, &rate);
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if (opp == ERR_PTR(-ERANGE)) {
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/*
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* Some clocks may be unused by a particular board and they
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* may have uninitiated clock rate that is overly high. In
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* this case clock is expected to be disabled, but still we
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* need to set up performance state of the power domain and
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* not error out clk initialization. A typical example is
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* a PCIe clock on Android tablets.
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*/
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dev_dbg(dev, "failed to find ceil OPP for %luHz\n", rate);
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opp = dev_pm_opp_find_freq_floor(dev, &rate);
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}
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if (IS_ERR(opp)) {
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dev_err(dev, "failed to find OPP for %luHz: %pe\n", rate, opp);
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return PTR_ERR(opp);
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}
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pstate = dev_pm_opp_get_required_pstate(opp, 0);
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dev_pm_opp_put(opp);
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return dev_pm_genpd_set_performance_state(dev, pstate);
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}
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static int tegra_clock_change_notify(struct notifier_block *nb,
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unsigned long msg, void *data)
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{
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struct clk_notifier_data *cnd = data;
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struct tegra_clk_device *clk_dev;
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int err = 0;
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clk_dev = container_of(nb, struct tegra_clk_device, clk_nb);
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mutex_lock(&clk_dev->lock);
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switch (msg) {
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case PRE_RATE_CHANGE:
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if (cnd->new_rate > cnd->old_rate)
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err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);
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break;
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case ABORT_RATE_CHANGE:
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err = tegra_clock_set_pd_state(clk_dev, cnd->old_rate);
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break;
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case POST_RATE_CHANGE:
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if (cnd->new_rate < cnd->old_rate)
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err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);
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break;
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default:
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break;
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}
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mutex_unlock(&clk_dev->lock);
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return notifier_from_errno(err);
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}
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static int tegra_clock_sync_pd_state(struct tegra_clk_device *clk_dev)
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{
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unsigned long rate;
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int ret;
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mutex_lock(&clk_dev->lock);
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rate = clk_hw_get_rate(clk_dev->hw);
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ret = tegra_clock_set_pd_state(clk_dev, rate);
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mutex_unlock(&clk_dev->lock);
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return ret;
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}
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static int tegra_clock_probe(struct platform_device *pdev)
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{
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struct tegra_core_opp_params opp_params = {};
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struct tegra_clk_device *clk_dev;
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struct device *dev = &pdev->dev;
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struct clk *clk;
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int err;
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if (!dev->pm_domain)
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return -EINVAL;
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clk_dev = devm_kzalloc(dev, sizeof(*clk_dev), GFP_KERNEL);
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if (!clk_dev)
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return -ENOMEM;
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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clk_dev->dev = dev;
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clk_dev->hw = __clk_get_hw(clk);
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clk_dev->clk_nb.notifier_call = tegra_clock_change_notify;
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mutex_init(&clk_dev->lock);
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platform_set_drvdata(pdev, clk_dev);
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/*
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* Runtime PM was already enabled for this device by the parent clk
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* driver and power domain state should be synced under clk_dev lock,
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* hence we don't use the common OPP helper that initializes OPP
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* state. For some clocks common OPP helper may fail to find ceil
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* rate, it's handled by this driver.
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*/
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err = devm_tegra_core_dev_init_opp_table(dev, &opp_params);
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if (err)
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return err;
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err = clk_notifier_register(clk, &clk_dev->clk_nb);
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if (err) {
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dev_err(dev, "failed to register clk notifier: %d\n", err);
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return err;
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}
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/*
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* The driver is attaching to a potentially active/resumed clock, hence
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* we need to sync the power domain performance state in a accordance to
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* the clock rate if clock is resumed.
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*/
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err = tegra_clock_sync_pd_state(clk_dev);
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if (err)
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goto unreg_clk;
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return 0;
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unreg_clk:
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clk_notifier_unregister(clk, &clk_dev->clk_nb);
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return err;
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}
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/*
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* Tegra GENPD driver enables clocks during NOIRQ phase. It can't be done
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* for clocks served by this driver because runtime PM is unavailable in
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* NOIRQ phase. We will keep clocks resumed during suspend to mitigate this
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* problem. In practice this makes no difference from a power management
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* perspective since voltage is kept at a nominal level during suspend anyways.
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*/
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static const struct dev_pm_ops tegra_clock_pm = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_resume_and_get, pm_runtime_put)
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};
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static const struct of_device_id tegra_clock_match[] = {
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{ .compatible = "nvidia,tegra20-sclk" },
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{ .compatible = "nvidia,tegra30-sclk" },
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{ .compatible = "nvidia,tegra30-pllc" },
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{ .compatible = "nvidia,tegra30-plle" },
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{ .compatible = "nvidia,tegra30-pllm" },
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{ }
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};
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static struct platform_driver tegra_clock_driver = {
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.driver = {
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.name = "tegra-clock",
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.of_match_table = tegra_clock_match,
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.pm = &tegra_clock_pm,
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.suppress_bind_attrs = true,
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},
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.probe = tegra_clock_probe,
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};
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builtin_platform_driver(tegra_clock_driver);
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@ -1914,7 +1914,7 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
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/* Data in .init is copied by clk_register(), so stack variable OK */
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pll->hw.init = &init;
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return clk_register(NULL, &pll->hw);
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return tegra_clk_dev_register(&pll->hw);
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}
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struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
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@ -226,7 +226,7 @@ struct clk *tegra_clk_register_super_mux(const char *name,
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/* Data in .init is copied by clk_register(), so stack variable OK */
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super->hw.init = &init;
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clk = clk_register(NULL, &super->hw);
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clk = tegra_clk_dev_register(&super->hw);
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if (IS_ERR(clk))
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kfree(super);
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@ -1158,7 +1158,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
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{ TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
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{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
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{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
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{ TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
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{ TEGRA114_CLK_VDE, TEGRA114_CLK_PLL_P, 408000000, 0 },
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{ TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
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{ TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
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{ TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
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@ -6,8 +6,11 @@
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/clk/tegra.h>
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#include <linux/delay.h>
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#include <dt-bindings/clock/tegra20-car.h>
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@ -414,7 +417,7 @@ static struct tegra_clk_pll_params pll_e_params = {
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.fixed_rate = 100000000,
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};
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static struct tegra_devclk devclks[] __initdata = {
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static struct tegra_devclk devclks[] = {
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{ .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
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{ .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
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{ .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
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@ -710,13 +713,6 @@ static void tegra20_super_clk_init(void)
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NULL);
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clks[TEGRA20_CLK_CCLK] = clk;
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/* SCLK */
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clk = tegra_clk_register_super_mux("sclk", sclk_parents,
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ARRAY_SIZE(sclk_parents),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
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clks[TEGRA20_CLK_SCLK] = clk;
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/* twd */
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clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
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clks[TEGRA20_CLK_TWD] = clk;
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@ -1014,7 +1010,7 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
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#endif
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};
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static struct tegra_clk_init_table init_table[] __initdata = {
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static struct tegra_clk_init_table init_table[] = {
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{ TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
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{ TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
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{ TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
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@ -1052,11 +1048,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
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{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
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};
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static void __init tegra20_clock_apply_init_table(void)
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{
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tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
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}
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/*
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* Some clocks may be used by different drivers depending on the board
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* configuration. List those here to register them twice in the clock lookup
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@ -1076,6 +1067,8 @@ static const struct of_device_id pmc_match[] __initconst = {
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{ },
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};
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static bool tegra20_car_initialized;
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static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
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void *data)
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{
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@ -1083,6 +1076,16 @@ static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
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struct clk_hw *hw;
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struct clk *clk;
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/*
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* Timer clocks are needed early, the rest of the clocks shouldn't be
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* available to device drivers until clock tree is fully initialized.
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*/
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if (clkspec->args[0] != TEGRA20_CLK_RTC &&
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clkspec->args[0] != TEGRA20_CLK_TWD &&
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clkspec->args[0] != TEGRA20_CLK_TIMER &&
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!tegra20_car_initialized)
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return ERR_PTR(-EPROBE_DEFER);
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clk = of_clk_src_onecell_get(clkspec, data);
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if (IS_ERR(clk))
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return clk;
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@ -1149,10 +1152,48 @@ static void __init tegra20_clock_init(struct device_node *np)
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tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
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tegra_add_of_provider(np, tegra20_clk_src_onecell_get);
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tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
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tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
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tegra_cpu_car_ops = &tegra20_cpu_car_ops;
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}
|
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CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
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CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
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/*
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* Clocks that use runtime PM can't be created at the tegra20_clock_init
|
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* time because drivers' base isn't initialized yet, and thus platform
|
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* devices can't be created for the clocks. Hence we need to split the
|
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* registration of the clocks into two phases. The first phase registers
|
||||
* essential clocks which don't require RPM and are actually used during
|
||||
* early boot. The second phase registers clocks which use RPM and this
|
||||
* is done when device drivers' core API is ready.
|
||||
*/
|
||||
static int tegra20_car_probe(struct platform_device *pdev)
|
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{
|
||||
struct clk *clk;
|
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|
||||
clk = tegra_clk_register_super_mux("sclk", sclk_parents,
|
||||
ARRAY_SIZE(sclk_parents),
|
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
||||
clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
|
||||
clks[TEGRA20_CLK_SCLK] = clk;
|
||||
|
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tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
|
||||
tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
|
||||
tegra20_car_initialized = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra20_car_match[] = {
|
||||
{ .compatible = "nvidia,tegra20-car" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver tegra20_car_driver = {
|
||||
.driver = {
|
||||
.name = "tegra20-car",
|
||||
.of_match_table = tegra20_car_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = tegra20_car_probe,
|
||||
};
|
||||
builtin_platform_driver(tegra20_car_driver);
|
||||
|
|
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|||
|
|
@ -7,8 +7,11 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
|
||||
#include <soc/tegra/pmc.h>
|
||||
|
|
@ -532,7 +535,7 @@ static unsigned long tegra30_input_freq[] = {
|
|||
[12] = 26000000,
|
||||
};
|
||||
|
||||
static struct tegra_devclk devclks[] __initdata = {
|
||||
static struct tegra_devclk devclks[] = {
|
||||
{ .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
|
||||
{ .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
|
||||
{ .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
|
||||
|
|
@ -812,11 +815,6 @@ static void __init tegra30_pll_init(void)
|
|||
{
|
||||
struct clk *clk;
|
||||
|
||||
/* PLLC */
|
||||
clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
|
||||
&pll_c_params, NULL);
|
||||
clks[TEGRA30_CLK_PLL_C] = clk;
|
||||
|
||||
/* PLLC_OUT1 */
|
||||
clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
|
||||
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
|
||||
|
|
@ -826,11 +824,6 @@ static void __init tegra30_pll_init(void)
|
|||
0, NULL);
|
||||
clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
|
||||
|
||||
/* PLLM */
|
||||
clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
|
||||
CLK_SET_RATE_GATE, &pll_m_params, NULL);
|
||||
clks[TEGRA30_CLK_PLL_M] = clk;
|
||||
|
||||
/* PLLM_OUT1 */
|
||||
clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
|
||||
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
|
||||
|
|
@ -880,9 +873,6 @@ static void __init tegra30_pll_init(void)
|
|||
ARRAY_SIZE(pll_e_parents),
|
||||
CLK_SET_RATE_NO_REPARENT,
|
||||
clk_base + PLLE_AUX, 2, 1, 0, NULL);
|
||||
clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
|
||||
CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
|
||||
clks[TEGRA30_CLK_PLL_E] = clk;
|
||||
}
|
||||
|
||||
static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
|
||||
|
|
@ -971,14 +961,6 @@ static void __init tegra30_super_clk_init(void)
|
|||
NULL);
|
||||
clks[TEGRA30_CLK_CCLK_LP] = clk;
|
||||
|
||||
/* SCLK */
|
||||
clk = tegra_clk_register_super_mux("sclk", sclk_parents,
|
||||
ARRAY_SIZE(sclk_parents),
|
||||
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
||||
clk_base + SCLK_BURST_POLICY,
|
||||
0, 4, 0, 0, NULL);
|
||||
clks[TEGRA30_CLK_SCLK] = clk;
|
||||
|
||||
/* twd */
|
||||
clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
|
|
@ -1214,7 +1196,7 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
static struct tegra_clk_init_table init_table[] = {
|
||||
{ TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
|
|
@ -1259,11 +1241,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static void __init tegra30_clock_apply_init_table(void)
|
||||
{
|
||||
tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
|
||||
}
|
||||
|
||||
/*
|
||||
* Some clocks may be used by different drivers depending on the board
|
||||
* configuration. List those here to register them twice in the clock lookup
|
||||
|
|
@ -1294,12 +1271,24 @@ static struct tegra_audio_clk_info tegra30_audio_plls[] = {
|
|||
{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
|
||||
};
|
||||
|
||||
static bool tegra30_car_initialized;
|
||||
|
||||
static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct clk *clk;
|
||||
|
||||
/*
|
||||
* Timer clocks are needed early, the rest of the clocks shouldn't be
|
||||
* available to device drivers until clock tree is fully initialized.
|
||||
*/
|
||||
if (clkspec->args[0] != TEGRA30_CLK_RTC &&
|
||||
clkspec->args[0] != TEGRA30_CLK_TWD &&
|
||||
clkspec->args[0] != TEGRA30_CLK_TIMER &&
|
||||
!tegra30_car_initialized)
|
||||
return ERR_PTR(-EPROBE_DEFER);
|
||||
|
||||
clk = of_clk_src_onecell_get(clkspec, data);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
|
|
@ -1357,10 +1346,75 @@ static void __init tegra30_clock_init(struct device_node *np)
|
|||
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
|
||||
|
||||
tegra_add_of_provider(np, tegra30_clk_src_onecell_get);
|
||||
tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
|
||||
|
||||
tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
|
||||
|
||||
tegra_cpu_car_ops = &tegra30_cpu_car_ops;
|
||||
}
|
||||
CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
|
||||
CLK_OF_DECLARE_DRIVER(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
|
||||
|
||||
/*
|
||||
* Clocks that use runtime PM can't be created at the tegra30_clock_init
|
||||
* time because drivers' base isn't initialized yet, and thus platform
|
||||
* devices can't be created for the clocks. Hence we need to split the
|
||||
* registration of the clocks into two phases. The first phase registers
|
||||
* essential clocks which don't require RPM and are actually used during
|
||||
* early boot. The second phase registers clocks which use RPM and this
|
||||
* is done when device drivers' core API is ready.
|
||||
*/
|
||||
static int tegra30_car_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
/* PLLC */
|
||||
clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
|
||||
&pll_c_params, NULL);
|
||||
clks[TEGRA30_CLK_PLL_C] = clk;
|
||||
|
||||
/* PLLE */
|
||||
clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
|
||||
CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
|
||||
clks[TEGRA30_CLK_PLL_E] = clk;
|
||||
|
||||
/* PLLM */
|
||||
clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
|
||||
CLK_SET_RATE_GATE, &pll_m_params, NULL);
|
||||
clks[TEGRA30_CLK_PLL_M] = clk;
|
||||
|
||||
/* SCLK */
|
||||
clk = tegra_clk_register_super_mux("sclk", sclk_parents,
|
||||
ARRAY_SIZE(sclk_parents),
|
||||
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
||||
clk_base + SCLK_BURST_POLICY,
|
||||
0, 4, 0, 0, NULL);
|
||||
clks[TEGRA30_CLK_SCLK] = clk;
|
||||
|
||||
tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
|
||||
tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
|
||||
tegra30_car_initialized = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra30_car_match[] = {
|
||||
{ .compatible = "nvidia,tegra30-car" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver tegra30_car_driver = {
|
||||
.driver = {
|
||||
.name = "tegra30-car",
|
||||
.of_match_table = tegra30_car_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = tegra30_car_probe,
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock driver must be registered before memory controller driver,
|
||||
* which doesn't support deferred probing for today and is registered
|
||||
* from arch init-level.
|
||||
*/
|
||||
static int tegra30_car_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra30_car_driver);
|
||||
}
|
||||
postcore_initcall(tegra30_car_init);
|
||||
|
|
|
|||
|
|
@ -9,14 +9,19 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
/* Global data of Tegra CPU CAR ops */
|
||||
static struct device_node *tegra_car_np;
|
||||
static struct tegra_cpu_car_ops dummy_car_ops;
|
||||
struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
|
||||
|
||||
|
|
@ -261,8 +266,8 @@ void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
|
|||
}
|
||||
}
|
||||
|
||||
void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
|
||||
struct clk *clks[], int clk_max)
|
||||
void tegra_init_from_table(struct tegra_clk_init_table *tbl,
|
||||
struct clk *clks[], int clk_max)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
|
|
@ -320,6 +325,8 @@ void __init tegra_add_of_provider(struct device_node *np,
|
|||
{
|
||||
int i;
|
||||
|
||||
tegra_car_np = np;
|
||||
|
||||
for (i = 0; i < clk_num; i++) {
|
||||
if (IS_ERR(clks[i])) {
|
||||
pr_err
|
||||
|
|
@ -348,7 +355,7 @@ void __init tegra_init_special_resets(unsigned int num,
|
|||
special_reset_deassert = deassert;
|
||||
}
|
||||
|
||||
void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
|
||||
void tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -372,6 +379,68 @@ struct clk ** __init tegra_lookup_dt_id(int clk_id,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static struct device_node *tegra_clk_get_of_node(struct clk_hw *hw)
|
||||
{
|
||||
struct device_node *np;
|
||||
char *node_name;
|
||||
|
||||
node_name = kstrdup(hw->init->name, GFP_KERNEL);
|
||||
if (!node_name)
|
||||
return NULL;
|
||||
|
||||
strreplace(node_name, '_', '-');
|
||||
|
||||
for_each_child_of_node(tegra_car_np, np) {
|
||||
if (!strcmp(np->name, node_name))
|
||||
break;
|
||||
}
|
||||
|
||||
kfree(node_name);
|
||||
|
||||
return np;
|
||||
}
|
||||
|
||||
struct clk *tegra_clk_dev_register(struct clk_hw *hw)
|
||||
{
|
||||
struct platform_device *pdev, *parent;
|
||||
const char *dev_name = NULL;
|
||||
struct device *dev = NULL;
|
||||
struct device_node *np;
|
||||
|
||||
np = tegra_clk_get_of_node(hw);
|
||||
|
||||
if (!of_device_is_available(np))
|
||||
goto put_node;
|
||||
|
||||
dev_name = kasprintf(GFP_KERNEL, "tegra_clk_%s", hw->init->name);
|
||||
if (!dev_name)
|
||||
goto put_node;
|
||||
|
||||
parent = of_find_device_by_node(tegra_car_np);
|
||||
if (parent) {
|
||||
pdev = of_platform_device_create(np, dev_name, &parent->dev);
|
||||
put_device(&parent->dev);
|
||||
|
||||
if (!pdev) {
|
||||
pr_err("%s: failed to create device for %pOF\n",
|
||||
__func__, np);
|
||||
goto free_name;
|
||||
}
|
||||
|
||||
dev = &pdev->dev;
|
||||
pm_runtime_enable(dev);
|
||||
} else {
|
||||
WARN(1, "failed to find device for %pOF\n", tegra_car_np);
|
||||
}
|
||||
|
||||
free_name:
|
||||
kfree(dev_name);
|
||||
put_node:
|
||||
of_node_put(np);
|
||||
|
||||
return clk_register(dev, hw);
|
||||
}
|
||||
|
||||
tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
|
||||
|
||||
static int __init tegra_clocks_apply_init_table(void)
|
||||
|
|
|
|||
|
|
@ -927,4 +927,6 @@ struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter);
|
|||
struct clk *tegra210_clk_register_emc(struct device_node *np,
|
||||
void __iomem *regs);
|
||||
|
||||
struct clk *tegra_clk_dev_register(struct clk_hw *hw);
|
||||
|
||||
#endif /* TEGRA_CLK_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue