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drm/i915: disable GT power saving early during system suspend 

Atm, we disable GT power saving during the end of the suspend sequence
in i915_save_state(). Doing the disabling at that point seems arbitrary.
One reason to disable it early though is to have a quiescent HW state
before we do anything else (for example save registers). So move the
disabling earlier, which also takes care canceling of the deferred RPS
enabling work done by intel_disable_gt_powersave().

Note that after the move we'll call intel_disable_gt_powersave() only
in case modeset is enabled, but that's anyway the only case where we
have it enabled in the first place.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Robert Beckett <robert.beckett@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Imre Deak 2014-05-12 18:35:05 +03:00 committed by Daniel Vetter
parent e494837aee
commit fe5b1886a7
2 changed files with 3 additions and 4 deletions
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5
drivers/gpu/drm/i915/i915_drv.c
View File

@ -524,10 +524,11 @@ static int i915_drm_freeze(struct drm_device *dev)
return error;
}
cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
drm_irq_uninstall(dev);
dev_priv->enable_hotplug_processing = false;
intel_disable_gt_powersave(dev);
/*
* Disable CRTCs directly since we want to preserve sw state
* for _thaw.

2
drivers/gpu/drm/i915/i915_suspend.c
View File

@ -328,8 +328,6 @@ int i915_save_state(struct drm_device *dev)
}
}
intel_disable_gt_powersave(dev);
/* Cache mode state */
if (INTEL_INFO(dev)->gen < 7)
dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);