Commit Graph

5 Commits

Author SHA1 Message Date
Boris BREZILLON 03a0e8a7c5 mtd: nand: sunxi: fix OOB handling in ->write_xxx() functions
The USER_DATA register cannot be accessed using byte accessors on A13
SoCs, thus triggering a bug when using memcpy_toio on this register.
Declare an helper macros to convert an OOB buffer into a suitable
USER_DATA value and vice-versa.

This patch also fixes an error in the oob_required logic (some OOB data
are not written even if the user required it) by removing the
oob_required condition, which is perfectly valid since the core already
fill ->oob_poi with FFs when oob_required is false.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: <stable@vger.kernel.org> # 3.19+
Fixes: 1fef62c142 ("mtd: nand: add sunxi NAND flash controller support")
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-09-21 13:36:42 -07:00
Roy Spliet d052e508a4 mtd: nand: sunxi: Set serial access mode correctly
Replaces the hard coded "always use EDO" policy with that prescribed
by the ONFI 3.1 specification that EDO mode should always be used if tRC
is below 30ns.

Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-07-20 10:45:53 -07:00
Roy Spliet 9c618292db mtd: nand: sunxi: Replace failsafe timing cfg with calculated value
The TIMING_CFG register was previously statically set to a magic value
(extracted from Allwinner's BSP) when initializing the NAND controller.
Now that we have more details about the TIMING_CFG register layout
(extracted from the A83 user manual) we can dynamically calculate the
appropriate value for each NAND chip and set it when selecting the
chip.

Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-07-20 10:45:52 -07:00
Aaron Sierra e0377cdeba mtd: nand: Request strength instead of bytes for soft BCH
Previously, we requested that drivers pass ecc.size and ecc.bytes when
using NAND_ECC_SOFT_BCH. However, a driver is likely to only know the ECC
strength required for its NAND, so each driver would need to perform a
strength-to-bytes calculation.

Avoid duplicating this calculation in each driver by asking drivers to
pass ecc.size and ecc.strength so that the strength-to-bytes calculation
need only be implemented once.

This reverts/generalizes this commit:
    mtd: nand: Base BCH ECC bytes on required strength

Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2015-02-01 21:10:58 -08:00
Boris BREZILLON 1fef62c142 mtd: nand: add sunxi NAND flash controller support
Add support for the sunxi NAND Flash Controller (NFC).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Brian: tweaked to fix ecc->steps issue]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-10-29 10:08:00 -07:00