This is a wrapper around the interfaces defined in an earlier commit,
and is also used by various userspace (either by a libdrm backend, or
libpciaccess) tools/tests.
In the future this will be extended to handle channels, replacing some
long-unloved code we currently use, and allow fifo/display/mpeg (hi
Ilia ;)) engines to all be exposed in the same way.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This forms the basis for the new APIs that will be exposed to userspace,
giving it access to:
- Object method calls, the immediately useful of which is performance
counters and the abiity to manipulate the ZBC tables.
- Information on the child classes an object supports, in order to avoid
having to try all supported classes until successful.
- Notifications, which will be used in the future to inform the client
if its channel was killed due to a lockup, etc.
This commit imports the interfaces, but are not currently used. The DRM
portion of the driver will be ported to speak to the core using these
interfaces as much as possible.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This is a lot of prep-work for being able to send event notifications
back to userspace. Events now contain data, rather than a "something
just happened" signal.
Handler data is now embedded into a containing structure, rather than
being kmalloc()'d, and can optionally have the notify routine handled
in a workqueue.
Various races between suspend/unload with display HPD/DP IRQ handlers
automagically solved as a result.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add support for reclocking on GK20A, using a statically-defined pstates
table. The algorithms for calculating the coefficients and setting the
clocks are directly taken from the ChromeOS kernel.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
GK20A's BAR is functionally identical to NVC0's, but do not support
being ioremapped write-combined. Create a BAR instance for GK20A that
reflect that state.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Add a platform driver for Nouveau devices declared using the device tree
or platform data. This driver currently supports GK20A on Tegra
platforms and is only compiled for these platforms if Nouveau is
enabled.
Nouveau will probe the chip type itself using the BOOT0 register, so all
this driver really needs to do is to make sure the module is powered and
its clocks active before calling nouveau_drm_platform_probe().
Heavily based on work done by Thierry Reding.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
As a side note.. It's a bit hard to figure out how to name this commit..
GK20A is NVEA, which is before NV108 (GK208).. Confusing.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
As documented at:
ftp://download.nvidia.com/open-gpu-doc/gk104-disable-graphics-power-gating/1/gk104-disable-graphics-power-gating.txt
NVIDIA were not able document the steps necessary to detect whether this
is required or not at this time. However, they did confirm that this
procedure is safe to perform unconditionally on GK104/6. GK107 does not
have the power gating feature, and it was recommended that we do not
perform these steps there as the effects were not verified.
The disable path is from observing the binary driver, and not
documented in the link above.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This will, at some point, be used to replace various bits and pieces of
code doing direct bios parsing. For now, it'll just be used for some
DP improvements.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
There's also provisions to allow a pad to be locked with a specific
routing, for an indefinite period of time. This will be used in
future patches.
The G94+ pad driver will now also power-down pads when not required.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add a simple FB device for GK20A, as well as a RAM implementation
suitable for chips that use system memory as video RAM.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
See https://bugs.freedesktop.org/show_bug.cgi?id=74492
Reported-by: Ronald <ronald645@gmail.com>
Suggested-by: Marcin Kościelnicki <koriakin@0x04.net>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This is what NVIDIA do on these chipsets, let's hope it works around
the reported MSI failures for us on NV86.
v2: updated to include G92, as per information provided by NVIDIA.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
v2. updated to cover GF104, as per information provided by NVIDIA.
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs