The memory controller clock runs either at half or the same frequency as
the EMC clock.
Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The "pcie_xclk" clock is not actually a clock at all, but rather a reset
domain. Now that the custom Tegra module reset API has been removed, we
can remove the definition of any "clocks" that existed solely to support
it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Create a header file to define the clock IDs used by the Tegra20 clock
binding. Remove the list of definitions from the binding documentation,
and refer the reader to the header file.
This will allow the same header to be used by both device tree files,
and drivers implementing this binding, which guarantees that the two
stay in sync. This also makes device trees more readable by using names
instead of magic numbers.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
[swarren, add header to clock/ instead of clk/ to match binding location]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding