Doing calibrate delay on a hardware thread will be inaccurate since
it depends on the load on other threads in the core. It will also
slow down the boot process when done for 128 hardware threads. Switch
to a pre-computed loops per jiffy based on the core frequency. The
value is computed based on the core frequency and roughly matches the
value calculated by calibrate_delay().
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4791/
Signed-off-by: John Crispin <blogic@openwrt.org>
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC
frequencey. One of these can be used as a clocksource to provide
timestamps that is common across cores. This can be used in place
of the count/compare clocksource which is per-CPU.
On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits
of the PIC counter. On XLP, the whole 64-bit can be used.
Provide common macros and functions for PIC timer registers on XLR/XLS
and XLP, and use them to register a PIC clocksource.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4786/
Signed-off-by: John Crispin <blogic@openwrt.org>
Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.
The L1 dcache is already split among the threads in the core.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/
Signed-off-by: John Crispin <blogic@openwrt.org>
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr()
and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations
and update the interrupt handling code to use these functions.
Also, use the EIMR register functions to mask interrupts in the
irq code.
The 64-bit interrupt request and mask registers (EIRR and EIMR) are
accessed when the interrupts are off, and the common operations are
to set or clear a bit in these registers. Using the 64-bit c0 access
functions for these operations is not optimal in 32-bit, because it
will disable/restore interrupts and split/join the 64-bit value during
each register access.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4790/
Signed-off-by: John Crispin <blogic@openwrt.org>
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
On XLR/XLS, the cpu cores communicate with fast on-chip devices
(e.g. network accelerator, security engine etc.) using the Fast
Messaging Network(FMN). The FMN queues and credits needs to be
configured and intialized before it can be used.
The co-processor 2 on XLR/XLS CPU cores has registers for FMN access,
and the XLR/XLS has custom instructions for sending and loading
messages. The FMN can deliver also per-cpu interrupts when messages
are available at the CPU.
This patch adds FMN initialization, adds interrupt setup and handling,
and also provides support for sending and receiving FMN messages.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4468
Signed-off-by: John Crispin <blogic@openwrt.org>
Create struct nlm_pic_irq for interrupts handled by the PIC.
This simplifies IRQ handling for multi-SoC as well as
the single SoC cases. Also split the setup of percpu and PIC
interrupts so that we can configure the PIC interrupts for
every node.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4467
Signed-off-by: John Crispin <blogic@openwrt.org>
Upto 4 Netlogic XLP SoCs can be connected over ICI links to form a
coherent multi-node system. Each SoC has its own set of on-chip
devices including PIC. To support this, add a per SoC stucture and
use it for the PIC and SYS block addresses instead of using global
variables.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4469
Signed-off-by: John Crispin <blogic@openwrt.org>
Initial code to support more than 32 cpus. The platform CPU mask
is updated from 32-bit mask to cpumask_t. Convert places that use
cpu_/cpus_ functions to use cpumask_* functions.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4464
Signed-off-by: John Crispin <blogic@openwrt.org>
The cpuid was not passed into early_init_secondary even though the
comment indicated that it will be. Fix this.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4458
Signed-off-by: John Crispin <blogic@openwrt.org>
Enable Speculative Unmap Enable bit, which will enable speculative L2
cache requests for unmapped memory. This should give better performance
for kernel code/data which is in KSEG0
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4461
Signed-off-by: John Crispin <blogic@openwrt.org>
In prom_putchar(), wait for just the TX empty bit to clear in the
UART LSR.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Cc: Florian Fainelli <florian@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/4112/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[ralf@linux-mips.org: I've folded most segments of this patch into those
patches in -next that originally were causing the whitespace damage.
This is just what's left over]
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4094/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Update for core intialization code. Initialize status register
after receiving NMI for CPU wakeup. Add the low level L1D flush
code before enabling threads in core.
Also convert the ehb to _ehb so that it works under more GCC
versions.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3755/
Patchwork: https://patchwork.linux-mips.org/patch/4095/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
No change in logic, comments update and whitespace cleanup.
* A few comments in the file were in assembler style and the rest
int C style, convert all of them to C style.
* Mark workarounds for Ax silicon with a macro XLP_AX_WORKAROUND
* Whitespace fixes - use tabs consistently
* rename __config_lsu macro to xlp_config_lsu
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3749/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This has been obsolescent for a while; time for the final push.
In adjacent context, replaced old cpus_* with cpumask_*.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Acked-by: David S. Miller <davem@davemloft.net> (arch/sparc)
Acked-by: Chris Metcalf <cmetcalf@tilera.com> (arch/tile)
Cc: user-mode-linux-devel@lists.sourceforge.net
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Richard Kuo <rkuo@codeaurora.org>
Cc: linux-hexagon@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Helge Deller <deller@gmx.de>
Cc: sparclinux@vger.kernel.org
Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.
If the chip is marked to be SMT capable, scheduler then could do more, say,
idle load balancing.
Changes are now confined only to the code of XLR, and hardware is probed
to get core ID for correct setup.
[jayachandranc: simplified and adapted for new merged XLR/XLP code]
Signed-off-by: Hillf Danton <dhillf@gmail.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2972/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Create a common NMI and reset handler in smpboot.S and use this for
both XLR and XLP. In the earlier code, the woken up CPUs would
busy wait until released, switch this to wakeup by NMI.
The initial wakeup code or XLR and XLP are differ since they are
started from different bootloaders (XLP from u-boot and XLR from
netlogic bootloader). But in both platforms the woken up CPUs wait
and are released by sending an NMI.
Add support for starting XLR and XLP in 1/2/4 threads per core.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2970/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
- Update common files to support XLP.
- Add arch/mips/include/asm/netlogic/xlp-hal for register definitions
and access macros
- Add arch/mips/netlogic/xlp/ for XLP specific files.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2967/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
- Move code that can be shared with XLP (irq.c, smp.c, time.c and
xlr_console.c) to arch/mips/netlogic/common
- Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and
io functions shared with XLP
- remove type 'nlm_reg_t *' and use uint64_t for mmio offsets
- Move XLR specific code in smp.c to xlr/wakeup.c
- Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c
- Provide API for pic functions called from common/irq.c
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2964/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle