Commit Graph

10 Commits

Author SHA1 Message Date
Andy Shevchenko cd5acb2bce pinctrl: geminilake: Provide Interrupt Status register offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:45:41 +03:00
Andy Shevchenko 6463955837 pinctrl: geminilake: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:41 +02:00
Andy Shevchenko ce96a3a041 pinctrl: geminilake: Sort register offsets by value
No functional change.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16 09:18:15 +02:00
Andy Shevchenko 2b3445c7eb pinctrl: geminilake: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

This patch converts the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16 09:18:15 +02:00
Andy Shevchenko 08a3e5dca0 pinctrl: geminilake: Update pin list for B0 stepping
According to an updated pin list few names of the pins can be spelled better,
taking into account their primary functions.

Thus, update a pin list to cover B0 stepping.

Note, SPI numbering had been fixed even in A0 public documentation.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16 09:17:18 +02:00
Andy Shevchenko 677506ee09 pinctrl: intel: Move linux/pm.h to the local header
We now using a common macro for PM operations in pin control drivers for Intel
SoCs, and since that macro relies on the definition and macro from linux/pm.h
header file, it's logical to include it directly in pinctrl-intel.h. Otherwise
it's a bit fragile and requires a proper ordering of header inclusion in C
files.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:37:19 -07:00
Andy Shevchenko 6016b099c3 pinctrl: geminilake: Define PM ops via INTEL_PINCTRL_PM_OPS()
Instead of open coding same structure definition for PM operations,
replace it with a common macro.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:43 +02:00
Andy Shevchenko 79b7d19eba pinctrl: geminilake: Convert to use intel_pinctrl_probe_by_uid()
Get rid of code duplication by converting to use intel_pinctrl_probe_by_uid().

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31 11:25:03 +02:00
Andy Shevchenko 875a92b3f5 pinctrl: intel: Convert to use SPDX identifier
Reduce size of duplicated comments by switching to use SPDX identifier.

No functional change.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-02 15:52:10 +02:00
Mika Westerberg 6693f9f96a pinctrl: intel: Add Intel Gemini Lake pin controller support
This driver adds pinctrl/GPIO support for Intel Gemini Lake SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.

This commit includes material from David E. Box.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-30 15:06:01 +01:00