Tweak the for loops that operate on the SIC IAR system MMRs to avoid
re-reading them multiple times in a row. System MMRs are a little
slower to access, so avoid the penalty when possible.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch removes a custom GPIO wakeup API which allowed GPIOs to act
as wakeup sources, which are not configured as Interrupts.
This API is a leftover from the time before irq_wake was established.
From now on people must use enable_irq_wake(GPIO_IRQx) and the GPIO in
question needs to be configured as Interrupt.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The on-chip keypad peripheral requires different registers to be setup
depending on the standby type (standby vs hibernation). However, since
the power management framework doesn't differentiate between these types,
the driver doesn't know which registers to program and subsequently it
avoids doing so.
Always enabling the keyboard wakeup source causes misbehavior when the
pins are not assigned to the keypad. If they happen to drive a certain
level, they'll trigger a wake up event which is not wanted. So until
the aforementioned issue can be sorted out, drop support for the
wakeup source completely.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch provides infrastructure for MAC Wake-On-Lan and PHYINT use in
phylib. New Interrupts added:
IRQ_MAC_PHYINT /* PHY_INT Interrupt */
IRQ_MAC_MMCINT /* MMC Counter Interrupt */
IRQ_MAC_RXFSINT /* RX Frame-Status Interrupt */
IRQ_MAC_TXFSINT /* TX Frame-Status Interrupt */
IRQ_MAC_WAKEDET /* Wake-Up Interrupt */
IRQ_MAC_RXDMAERR /* RX DMA Direction Error Interrupt */
IRQ_MAC_TXDMAERR /* TX DMA Direction Error Interrupt */
IRQ_MAC_STMDONE /* Station Mgt. Transfer Done Interrupt */
On BF537/6 the implementation is not straight forward since there are now
two chained chained_handlers. A cleaner approach would have been to add
latter IRQs to the demux of IRQ_GENERIC_ERROR.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This makes room for off-chip IRQ controllers.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
SMP systems require per-cpu local clock event devices in order to enable
HRT support. One a BF561, we can use local core timer for this purpose.
Originally, there was one global core-timer clock event device set up for
core A.
To accomplish this feat, we need to split the gptimer0/core timer logic
so that each is a standalone clock event. There is no requirement that
we only have one clock event source anyways. Once we have this, we just
define per-cpu clock event devices for each local core timer.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that the Blackfin IRQ controller supports this, drivers get the normal
functionality of controlling which CPU to bind IRQs to.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The error masks are only needed in the BF537 demux error code, so instead
of needing all the short peripheral defines in global space, push these
masks into the one file where they are actually needed. This fixes a
bunch of define collisions with common code (can/serial/etc...).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Barry Song <barry.song@analog.com>
Bill Gatliff & David Brownell pointed out we were missing some
copyrights, and licensing terms in some of the files in
./arch/blackfin, so this fixes things, and cleans them up.
It also removes:
- verbose GPL text(refer to the top level ./COPYING file)
- file names (you are looking at the file)
- bug url (it's in the ./MAINTAINERS file)
- "or later" on GPL-2, when we did not have that right
It also allows some Blackfin-specific assembly files to be under a BSD
like license (for people to use them outside of Linux).
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The purpose of the EVT14 handler may depend on whether CONFIG_IPIPE is
enabled, albeit its implementation can be the same in both cases. When
the interrupt pipeline is enabled, EVT14 can be used to raise the core
priority level for the running code; when CONFIG_IPIPE is off, EVT14
can be used to lower this level before running softirq handlers.
Rename evt14_softirq to evt_evt14 to pick an identifier that fits
both, which allows to reuse the same vector setup code as well.
Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Convert to test_bit() as that is what pretty much everyone uses and allows
us to migrate asm/bitops.h to the asm-generic version.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Rather than having to maintain a hard coded list of Blackfin variants, use
the SIC defines themselves. This fixes build problems on BF51x/BF538 under
some configurations as they were missing from one of the lists.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
For systems where the core cycles are not a usable tick source (like SMP
or cycles gets updated), enable gptimer0 as an alternative.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
ipipe-2.6.28.9-blackfin-git95aafe6.patch
Singed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
base SIC_IWR# programming on whether the MMR exists
rather than having to maintain another list of processors
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
[Mike Frysinger <vapier.adi@gmail.com>:
- handle bf531/bf532/bf534/bf536 variants in ipipe.h
- cleanup IPIPE logic for bfin_set_irq_handler()
- cleanup ipipe asm code a bit and add missing ENDPROC()
- simplify IPIPE code in trap_c
- unify some of the IPIPE code and fix style
- simplify DO_IRQ_L1 handling with ipipe code
- revert IRQ_SW_INT# addition from ipipe merge
- remove duplicate get_{c,s}clk() prototypes
]
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
[Mike Frysinger <vapier.adi@gmail.com>:
- use KERN_NOTICE when using gpios as both irq and non
rather than KERN_ERR
- embedded newlines in printk() does not fly]
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
rename irq_flags to bfin_irq_flags to avoid namespace
collision with common code
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like
In this patch, we provide SMP extend to Blackfin header files
and machine common code
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Remove SSYNC()
- Use irq_to_gpio where applicable
- Remove gpio_edge_triggered bitfield, check irq_desc fields instead.
- Remove gpio_both_edge_triggeredb bitfield, check irq_desc fields
instead.
- Use BITMAP and bitops on gpio_enabled
- Preferably use 32-bit
- Looking at the disassembly this indeed saves quite a few instructions.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- remove SSYNC() left over from irq init split
- do not force SSYNC() when masking/unmasking IRQs in the SIC
as any order enforced by the hardware should already be enforced
by software
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The whole story:
Before BF51x merged, all the MAX_BLACKFIN_GPIOS are integral multiple of GPIO_BANKSIZE (= 16).
But BF51x provides MAX_BLACKFIN_GPIOS = 40 which includes 3 banks and the 3rd bank has only 8
GPIO pins.
Therefore, gpio_bank() macros is correct when you try to find a GPIO in which bank (GPIO_35 is
in bank 2). But on BF51x gpio_bank(MAX_BLACKFIN_GPIOS) only gives out 2 banks instead of 3
banks for some static array initialization.
This patch add a new macros gpio_bank_n() and GPIO_BANK_NUM to do bank number caculating and
remain the gpio_bank() macros for positioning a gpio in which bank.
Signed-off-by: Bryan Wu <cooloney@kernel.org>
- Disable all bits in SIC_IWR unless we are going into a real (DPMC)
power saving mode. Any Interrupt can wake the core form it's idle state.
- Remove deep sleep mode as it is not going to be used anywhere:
We support sleep, sleep deeper and hibernate.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Remove the circular buffering mechanism for exceptions. Instead, point RETX
at a safe location from which to fetch three NOPs.
This safe location is now in the fixed code area, and also used for certain
anomaly workarounds, to ensure that user space can find a valid ICPLB when
things are built with CONFIG_MPU.
Also, save I/DCPLB_FAULT_ADDRESS when lowering to level 5, since the hardware
reg is valid only at exception level.
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
The irq setup code no longer calls gpio request and free.
This patch also changes the default gpio_free behavior on Blackfin.
A freed GPIO keeps it's last state, and is not defaulted back to
an input. This is also what all other architectures do.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Mike Frysinger