side. The two main highlights in the core framework are the addition of an bulk
clk_get API that handles optional clks and an extra debugfs file that tells the
developer about the current parent of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is mostly
because that SoC has started converting to the clk_hw style of clk
registration. The next big update is in the Amlogic meson clk driver that
gained some support for audio, cpu, and temperature clks while fixing some PLL
issues. Finally, the biggest thing that stands out is the conversion of a large
part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses
less strings and more pointer comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks here and
there to clk data along with the normal addition of a handful of new drivers
and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl0uBEERHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSWucw/9ELKlfvdxrc8mdIuzt+CpKdNiSG88shXY
hF+vnuE6Jhv5hmlbA/DbplPTAnHT/FQF65/GPQMAYy2wYO6CjleNxQyepiVv4h8/
tWoXu5vYZXubtQyMnYTffREzjYFPBNAscLUhXNwJKRno7nT0qKCk62WgOMfaW/KN
lP5dKmrL7rdJDUvxHEStrwP515Lg5Wkhj3+XzgbgFUKGuGlvHfwUOEZucT++kqhu
Z1vMjPv2ksHQf3r15BsbX/6jMIONEt2Xd6jA3Lm7ebDXJl2hjX4Gq0Kkl5pmkj2w
F0V7Tw4XYk6DkSl7HQaOBgQ8KV0Mw2L8Vj6eEDhUwx6wPGlQ5YTKkUCJkjs0mUyb
UpO3TuPFN2W0hsTNDzwYpjqcfodDn159XJcduv1/ZpIanUvHgx0uVzQ7iwwYwW+l
VR4SipY5AEn9hpief30X7TAUSKsE4do58imYeoGBrq78zdsJaEcDAMX7AcYdXVQ9
ahBS8ME/d1JEBNdRsSW7eTAfu8dZdI08uR8/T37GRG59XyZSjsyVmZ6kHCYrBygF
AyLNMsXMCbW1rOoIpWkuGMD86XZy40laLg8T7WWTaq28t1VQ0BaBTGM4/eEexs3p
FhZ1M7aH+PsDLrI2IGTBt/4xAMv+dhDS7HnxRlOONbWnLWVqmR+tYzF0aCkqJCmd
O2zWCGffeYs=
=mK0C
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This round of clk driver and framework updates is heavy on the driver
update side. The two main highlights in the core framework are the
addition of an bulk clk_get API that handles optional clks and an
extra debugfs file that tells the developer about the current parent
of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is
mostly because that SoC has started converting to the clk_hw style of
clk registration. The next big update is in the Amlogic meson clk
driver that gained some support for audio, cpu, and temperature clks
while fixing some PLL issues. Finally, the biggest thing that stands
out is the conversion of a large part of the Allwinner sunxi-ng driver
to the new clk parent scheme that uses less strings and more pointer
comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks
here and there to clk data along with the normal addition of a handful
of new drivers and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
clk: consoldiate the __clk_get_hw() declarations
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: at91: sckc: add support for SAM9X60
...
The first part of ongoing work to convert the sunxi-ng clk driver from
using global clock name strings to describe clk parenting, to having
direct struct clk_hw pointers, or local names based on clock-names from
the device tree binding.
This is based on Stephen Boyd's recent work allowing clk drivers to
specify clk parents using struct clk_hw * or parsing DT phandles in the
clk node.
This series can be split into a few major parts:
1) The first patch is a small fix for clk debugfs representation.
2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
situations I encountered, or assume I will encounter, such as single
internal (struct clk_hw *) parent, single DT (struct clk_parent_data
.fw_name), multiple internal parents, and multiple mixed (internal +
DT) parents. A special variant for just an internal single parent is
added, CLK_HW_INIT_HWS, which lets the driver share the singular
list, instead of having the compiler create a compound literal every
time. It might even make sense to only keep this variant.
3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
is the same as the single parent CLK_HW_INIT_* helpers.
4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
either struct clk_hw * or DT .fw_name types, whichever the hardware
requires.
5) The beginning of SUNXI_CCU_GATE conversion to local parent
references. This part is not done. They are included as justification
and examples for the shared list of clk parents case.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAl0NkFUOHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDDs1A/8CxGjEgNUYTQZRfJRdOXARlfwBcejVbBt4YUV
/BX4weCyrViT/9feOcHlalfdvleG7B3bmB7Q9s7M/UjDDL6uikoIw49idPqF5MLS
ZK0O+rz4Ok5vsmAkn0cyeDy3W7difWA9/5ic+diLzonjl4j/isQIgiiaIUrjZ35w
2LnFKLNPHhzfohNP8RdgvMUnZEric/4X5gx6cKUKMx5bBH2gyNaGxqYh5rq5o792
63SpACc/sMpfhGHyY1c8SPqlL1HR6K6C5Ecp+jvc9Es7mdVeea1fF0qetNt5ZeH2
kmvA3tWu7Dsy5yLcr/KLLdQjBfrg8dgcDC97t/Ks+u//QeKGaSqho6PskM+BwbnO
kxSwziVcZC2ZQDjtB4VtLzcw1Td4Sph2+Q7Lt9MeDrLS3pwpimVLS6AtZZ9YIHWg
tLh2FyxvZRhS/8h8pVb5LiJKqEx2q7e689fVuHAzmEFAiD0nHDzyDbVIjGM7Hqgd
wp5pTi5NaZhAA416NjaZspzGXhuXubgg72zx9yaFtnrgdEHbCbmdCeAU8fubpcdr
GAdrMG9k7Fn3Kr/bSXPTzjIlNuSQrB0Tzs6YP090DzaYSs05DbWh4KPVW5eOhjld
vVXAb6O4467Hcn70hWoN17m2kFpWEE1C9aQbb2m7BexyXqtqsfaZqnCwP2HTLAZJ
xBAOxqU=
=VdZo
-----END PGP SIGNATURE-----
Merge tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner sunxi-ng clk driver parent relation rewrite part 1 - take 2
from Chen-Yu Tsai:
"The first part of ongoing work to convert the sunxi-ng clk driver from
using global clock name strings to describe clk parenting, to having
direct struct clk_hw pointers, or local names based on clock-names from
the device tree binding.
This is based on Stephen Boyd's recent work allowing clk drivers to
specify clk parents using struct clk_hw * or parsing DT phandles in the
clk node.
This series can be split into a few major parts:
1) The first patch is a small fix for clk debugfs representation.
2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
situations I encountered, or assume I will encounter, such as single
internal (struct clk_hw *) parent, single DT (struct clk_parent_data
.fw_name), multiple internal parents, and multiple mixed (internal +
DT) parents. A special variant for just an internal single parent is
added, CLK_HW_INIT_HWS, which lets the driver share the singular
list, instead of having the compiler create a compound literal every
time. It might even make sense to only keep this variant.
3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
is the same as the single parent CLK_HW_INIT_* helpers.
4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
either struct clk_hw * or DT .fw_name types, whichever the hardware
requires.
5) The beginning of SUNXI_CCU_GATE conversion to local parent
references. This part is not done. They are included as justification
and examples for the shared list of clk parents case."
* tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (25 commits)
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: gate: Add macros for referencing local clock parents
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
clk: fixed-factor: Add CLK_FIXED_FACTOR_HWS which takes list of struct clk_hw *
...
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_HWS
as the parent clock is internal to this clock unit.
To avoid duplication of clock definitions, we fix up the parent
reference for A83T in the A83T init function.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_DATA to
specify the parent clock.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw,
and .parent_data, for clk drivers to specify parents using a combination
of device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.
Add four new macros:
- SUNXI_CCU_GATE_HW, that can take a struct clk_hw pointer, instead
of a string, as its parent.
- SUNXI_CCU_GATE_FW that takes a string to match a clock-names entry
in the device tree to specify the clock parent.
- SUNXI_CCU_GATE_HWS that takes an array of struct clk_hw * as its
parent. This allows the array to be shared with other clk
declarations.
- SUNXI_CCU_GATE_DATA that takes an array of struct clk_parent_data *
as its parent. This allows the array to be shared with other clk
declarations.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
A forward declaration for struct clk_fixed_factor pll_periph0_4x_clk
is added as the definitions of the fixed factor clocks appear much later
in the file. The position of fixed factor clock definitions will be
moved for all drivers at a later time, before the conversion of all
other clock types.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code and CLK_HW_INIT_* macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing CLK_HW_INIT_* definitions to describe parents using
either struct clk_hw pointers or clock-names from the device tree
binding.
For the AR100, this also allows us to merge the generic AR100 and the
A83T specific one, which only differed in the global clock names for
their parent clocks. The device tree bindings used the same name
specifiers.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Commit 89a5ddcc79 ("clk: Add of_clk_hw_register() API for early clk
drivers") introduces a new API for registering clks, which allows the
user to directly specify a device node, even if there is no struct
device attached to it. The device node is used for local DT clock-names
matching.
Switch to of_clk_hw_register() so that local DT clock-names matching
works.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Based on 1 normalized pattern(s):
this software is licensed under the terms of the gnu general public
license version 2 as published by the free software foundation and
may be copied distributed and modified under those terms this
program is distributed in the hope that it will be useful but
without any warranty without even the implied warranty of
merchantability or fitness for a particular purpose see the gnu
general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 285 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Fixes: b7c7b05065 ("clk: sunxi-ng: add support for H6 PRCM CCU")
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Based on 3 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version [author] [kishon] [vijay] [abraham]
[i] [kishon]@[ti] [com] this program is distributed in the hope that
it will be useful but without any warranty without even the implied
warranty of merchantability or fitness for a particular purpose see
the gnu general public license for more details
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version [author] [graeme] [gregory]
[gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i]
[kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema]
[hk] [hemahk]@[ti] [com] this program is distributed in the hope
that it will be useful but without any warranty without even the
implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 1105 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 3029 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
- Support for Cirrus Logic Lochnagar clks
* clk-hisi:
clk: hi3660: Mark clk_gate_ufs_subsys as critical
* clk-lochnagar:
clk: lochnagar: Add support for the Cirrus Logic Lochnagar
clk: lochnagar: Add initial binding documentation
* clk-allwinner:
clk: sunxi-ng: sun5i: Export the MBUS clock
clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
clk: sunxi-ng: h6: Preset hdmi-cec clock parent
clk: sunxi: Add Kconfig options
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
clk: sunxi-ng: Allow DE clock to set parent rate
* clk-rockchip:
clk: rockchip: undo several noc and special clocks as critical on rk3288
clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288
clk: rockchip: Limit use of USB PHY clock to USB on rk3288
clk: rockchip: Fix video codec clocks on rk3288
clk: rockchip: Make rkpwm a critical clock on rk3288
clk: rockchip: fix wrong clock definitions for rk3328
* clk-qoriq:
clk: qoriq: increase array size of cmux_to_group
dt-bindings: qoriq-clock: Add ls1028a chip compatible string
clk: qoriq: Add ls1028a clock configuration
clk: qoriq: add more PLL divider clocks support
dt-bindings: qoriq-clock: add more PLL divider clocks support
This patch corrects the SPDX License Identifier style
in header files related to Clock Drivers for Allwinner SoCs.
For C header files Documentation/process/license-rules.rst
mandates C-like comments (opposed to C source files where
C++ style should be used)
Changes made by using a script provided by Joe Perches here:
https://lkml.org/lkml/2019/2/7/46
Suggested-by: Joe Perches <joe@perches.com>
Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The MBUS clock is used by the MBUS controller, so let's export it so that
we can use it in our DT node.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Allwinner's BSP for the A83T lists pll-video0 as the first parent to
csi-mclk with index 0. This parent is not listed in the datasheet, but
actually works, and makes more sense considering the index is the
default value out of reset.
Add pll-video0 as a parent to csi-mclk with index 0.
Fixes: 05359be117 ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add an explanation why zero width check is needed when generating factor
mask using GENMASK() macro.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Video related clocks need to set rate as close as possible to the
requested one, so they should be able to change parent clock rate.
When processing 4K video, VPU clock has to be set to higher rate than it
is default parent rate. Because of that, VPU clock should be able to
change parent clock rate.
Add CLK_SET_RATE_PARENT flag to tcon-lcd0, tcon-tv0 and ve.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
H6 manual and BSP clock driver both states that hdmi-cec clock has two
possible parents, osc32k and pll-periph0-2x with 36621 predivider.
Because pll-periph0-2x is always 1.2 GHz, both parents give same
hdmi-cec rate - 32768 Hz, which is exactly the rate needed for HDMI CEC
controller to operate correctly.
However, for some reason, HDMI CEC controller doesn't work if default
parent (osc32k) is used. BSP HDMI driver also always use pll-periph0-2x
as hdmi-cec clock parent.
In order to solve the issue, preset hdmi-cec clock parent to
pll-periph0-2x.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Sometimes one of the nkmp factors is unused. This means that one of the
factors shift and width values are set to 0. Current nkmp clock code
generates a mask for each factor with GENMASK(width + shift - 1, shift).
For unused factor this translates to GENMASK(-1, 0). This code is
further expanded by C preprocessor to final version:
(((~0UL) - (1UL << (0)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (-1))))
or a bit simplified:
(~0UL & (~0UL >> BITS_PER_LONG))
It turns out that result of the second part (~0UL >> BITS_PER_LONG) is
actually undefined by C standard, which clearly specifies:
"If the value of the right operand is negative or is greater than or
equal to the width of the promoted left operand, the behavior is
undefined."
Additionally, compiling kernel with aarch64-linux-gnu-gcc 8.3.0 gave
different results whether literals or variables with same values as
literals were used. GENMASK with literals -1 and 0 gives zero and with
variables gives 0xFFFFFFFFFFFFFFF (~0UL). Because nkmp driver uses
GENMASK with variables as parameter, expression calculates mask as ~0UL
instead of 0. This has further consequences that LSB in register is
always set to 1 (1 is neutral value for a factor and shift is 0).
For example, H6 pll-de clock is set to 600 MHz by sun4i-drm driver, but
due to this bug ends up being 300 MHz. Additionally, 300 MHz seems to be
too low because following warning can be found in dmesg:
[ 1.752763] WARNING: CPU: 2 PID: 41 at drivers/clk/sunxi-ng/ccu_common.c:41 ccu_helper_wait_for_lock.part.0+0x6c/0x90
[ 1.763378] Modules linked in:
[ 1.766441] CPU: 2 PID: 41 Comm: kworker/2:1 Not tainted 5.1.0-rc2-next-20190401 #138
[ 1.774269] Hardware name: Pine H64 (DT)
[ 1.778200] Workqueue: events deferred_probe_work_func
[ 1.783341] pstate: 40000005 (nZcv daif -PAN -UAO)
[ 1.788135] pc : ccu_helper_wait_for_lock.part.0+0x6c/0x90
[ 1.793623] lr : ccu_helper_wait_for_lock.part.0+0x48/0x90
[ 1.799107] sp : ffff000010f93840
[ 1.802422] x29: ffff000010f93840 x28: 0000000000000000
[ 1.807735] x27: ffff800073ce9d80 x26: ffff000010afd1b8
[ 1.813049] x25: ffffffffffffffff x24: 00000000ffffffff
[ 1.818362] x23: 0000000000000001 x22: ffff000010abd5c8
[ 1.823675] x21: 0000000010000000 x20: 00000000685f367e
[ 1.828987] x19: 0000000000001801 x18: 0000000000000001
[ 1.834300] x17: 0000000000000001 x16: 0000000000000000
[ 1.839613] x15: 0000000000000000 x14: ffff000010789858
[ 1.844926] x13: 0000000000000000 x12: 0000000000000001
[ 1.850239] x11: 0000000000000000 x10: 0000000000000970
[ 1.855551] x9 : ffff000010f936c0 x8 : ffff800074cec0d0
[ 1.860864] x7 : 0000800067117000 x6 : 0000000115c30b41
[ 1.866177] x5 : 00ffffffffffffff x4 : 002c959300bfe500
[ 1.871490] x3 : 0000000000000018 x2 : 0000000029aaaaab
[ 1.876802] x1 : 00000000000002e6 x0 : 00000000686072bc
[ 1.882114] Call trace:
[ 1.884565] ccu_helper_wait_for_lock.part.0+0x6c/0x90
[ 1.889705] ccu_helper_wait_for_lock+0x10/0x20
[ 1.894236] ccu_nkmp_set_rate+0x244/0x2a8
[ 1.898334] clk_change_rate+0x144/0x290
[ 1.902258] clk_core_set_rate_nolock+0x180/0x1b8
[ 1.906963] clk_set_rate+0x34/0xa0
[ 1.910455] sun8i_mixer_bind+0x484/0x558
[ 1.914466] component_bind_all+0x10c/0x230
[ 1.918651] sun4i_drv_bind+0xc4/0x1a0
[ 1.922401] try_to_bring_up_master+0x164/0x1c0
[ 1.926932] __component_add+0xa0/0x168
[ 1.930769] component_add+0x10/0x18
[ 1.934346] sun8i_dw_hdmi_probe+0x18/0x20
[ 1.938443] platform_drv_probe+0x50/0xa0
[ 1.942455] really_probe+0xcc/0x280
[ 1.946032] driver_probe_device+0x54/0xe8
[ 1.950130] __device_attach_driver+0x80/0xb8
[ 1.954488] bus_for_each_drv+0x78/0xc8
[ 1.958326] __device_attach+0xd4/0x130
[ 1.962163] device_initial_probe+0x10/0x18
[ 1.966348] bus_probe_device+0x90/0x98
[ 1.970185] deferred_probe_work_func+0x6c/0xa0
[ 1.974720] process_one_work+0x1e0/0x320
[ 1.978732] worker_thread+0x228/0x428
[ 1.982484] kthread+0x120/0x128
[ 1.985714] ret_from_fork+0x10/0x18
[ 1.989290] ---[ end trace 9babd42e1ca4b84f ]---
This commit solves the issue by first checking value of the factor
width. If it is equal to 0 (unused factor), mask is set to 0, otherwise
GENMASK() macro is used as before.
Fixes: d897ef56fa ("clk: sunxi-ng: Mask nkmp factors when setting register")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
Fix this problem.
Fixes: 0380126eb9 ("clk: sunxi-ng: add support for suniv F1C100s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
DE2/DE3 mixers have to run at specific frequency in order to work
optimally. This wasn't actually possible for some SoCs because "de"
clock wasn't allowed to adjust parent rate.
Add CLK_SET_RATE_PARENT flag to all "de" clocks which didn't have it
yet.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.
Fix the gate bit definitions in the clock driver.
Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.
Add the 2 LDO enable bits to the gate bits.
Fixes: 5690879d93 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
According to the datasheet and the reference code from Allwinner, the
bit used to de-assert the TCON reset is bit 4, not bit 3.
Fix it in the V3s CCU driver.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cedrus driver wants to set VE clock higher than it's possible without
changing parent rate.
Allow changing parent rate for VE clock, so clock rate can be set
freely.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
All the audio interfaces on Allwinner SoCs need to change their module
clocks during operation, to switch between support for 44.1 kHz and 48
kHz family sample rates. The clock rate for the module clocks is
governed by their upstream audio PLL. The module clocks themselves only
have a gate, and sometimes a divider or mux. Thus any rate changes need
to be propagated upstream.
Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve
this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The audio blocks require specific clock rates. Until now we were using
the closest clock rate possible with integer N-M factors. This resulted
in audio playback being slightly slower than it should be.
The vendor kernel gets around this (for newer SoCs) by using sigma-delta
modulation to generate a fractional-N factor. As the PLL hardware is
identical in most chips, we can back port the settings from the newer
SoC, in this case the H3, onto the A33.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cedrus driver wants to set VE clock higher than it's possible without
changing parent rate.
In order to correct that, allow changing parent rate for VE clock.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The suniv F1C100s SoC (the chip in some new F-series products of
Allwinner)
has a CCU which seems to be a stripped version of the CCU in SoCs after
sun6i.
Add support for the CCU.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The third parent of CSI_MCLK is PLL_PERIPH1, not PLL_PERIPH0.
Fix it.
Fixes: 0577e4853b ("clk: sunxi-ng: Add H3 clocks")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
On the R40, in addition to a mux between the RTC's own RC oscillator and
an external 32768 Hz crystal, which are muxed inside the RTC module, the
CCU also has its own RC oscillator, which runs at around 2 MHz, and can
be muxed with the LOSC output from the RTC. This muxed output is called
"SYS 32K" in the module clock diagram, but otherwise referred to as the
LOSC throughout the CCU documentation.
The RC oscillator is not very accurate, even though it has an undocumented
calibration function. We really want a precise clock at 32768 Hz,
instead of something at around 32 KHz. This patch forces the SYS 32K
clock to use the RTC output as its parent, and doesn't bother
registering the internal oscillator nor a clock mux.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The audio blocks require specific clock rates. Until now we were using
the closest clock rate possible with integer N-M factors. This resulted
in audio playback being slightly slower than it should be.
The vendor kernel gets around this (for some SoCs) by using sigma-delta
modulation to generate a fractional-N factor. As the PLL hardware is
identical in most chips, we can port the settings for H3 onto the A64.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Linus Torvalds