Handle errata (it was unintentional on this h/w, whereas its intentional
on others) whereby the nIEN bit in Device Control is ignored, leading to
a situation where a hardware interrupt completes the qc before the
polling code has a chance to.
This will get fixed The Right Way(tm) once Albert Lee's irq-pio
branch is merged, as the more natural PIO method on this hardware is
interrupt-driven.
- DMA boundary was being handled incorrectly. Copied the code from
ata_fill_sg(), since Marvell has the same DMA boundary needs.
(we can't use ata_fill_sg directly since we have different hardware
descriptors)
- cleaned up the SATA phy reset code, to deal with various errata
Use ata_pad_{alloc,free} in two drivers, to factor out common code.
Add ata_pad_{alloc,free} to two other drivers, which needed the padding
but had not been updated.
The second argument to ata_qc_complete() was being used for two
purposes: communicate the ATA Status register to the completion
function, and indicate an error. On legacy PCI IDE hardware, the latter
is often implicit in the former. On more modern hardware, the driver
often completely emulated a Status register value, passing ATA_ERR as an
indication that something went wrong.
Now that previous code changes have eliminated the need to use drv_stat
arg to communicate the ATA Status register value, we can convert it to a
mask of possible error classes.
This will lead to more flexible error handling in the future.
Jeff found an endian bug in the Marvell driver (thanks!). Here's the
fix for it.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This should fix up lockups that people were seeing due to
improper spinlock placement. Also, the start/stop DMA routines put
guarded trust in the cached state of DMA.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This is my libata compatible low level driver for the Marvell SATA
family. Currently it runs in DMA mode on a 6081 chip.
The 5xxx series parts are not yet DMA capable in this driver because
the registers have differences that haven't been accounted for yet.
Basically, I'm focused on the 6xxx series right now. I apologize for
those seeing problems on the 5xxx series, I've not had a chance to
look at those problems yet.
For those curious, the previous bug causing the SCSI timeout and
subsequent panics was caused by an improper clear of hc_irq_cause in
mv_host_intr().
This version is running well in my environment (6081 chips,
with/without SW raid1) and is showing equal or better performance
compared to the Marvell driver (mv_sata) in my initial tests (timed
dd's of reads/writes to/from memory/disk).
I still need to look at the causes of occasional problems such as this:
ata11: translating stat 0x35 err 0x00 to sense
ata11: status=0x35 { DeviceFault SeekComplete CorrectedError Error }
SCSI error : <10 0 0 0> return code = 0x8000002
Current sda: sense key Hardware Error
end_request: I/O error, dev sda, sector 3155010
and this, seen at init time:
ATA: abnormal status 0x80 on port 0xE093911C
but they aren't showstoppers.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
libata.h:
libata-core:
Add ATA_FLAG_PIO_POLLING flag for LLDs that expect interrupt for
command completion only.
sata_nv.c:
sata_vsc.c:
irq handler is wrapper around ata_host_intr(), can handle PIO interrupts.
sata_promise.c:
sata_sx4.c:
sata_qstor.c:
sata_mv.c:
Private irq handler.
Polling mode ATA_FLAG_PIO_POLLING used for compatibility.
Signed-off-by: Albert Lee <albertcc@tw.ibm.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This is my libata compatible low level driver for the Marvell SATA
family. Currently it successfully runs in PIO mode on a 6081 chip.
EDMA support is in the works and should be done shortly. Review,
testing (especially on other flavors of Marvell), comments welcome.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Jeff Garzik