In (93bfb76 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock. We properly marked
exynos4_read_sched_clock() as notrace. However, we then went and
called another function that _wasn't_ notrace. That means if you do:
cd /sys/kernel/debug/tracing/
echo function_graph > current_tracer
You'll get a crash.
Fix this (but still let other readers of the MCT be trace-enabled) by
adding an extra function. It's important to keep other users of MCT
traceable because the MCT is actually quite slow to access and we want
exynos4_frc_read() to show up in ftrace profiles if it's the
bottleneck.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Document DT bindings and parse them in the MTU2 driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Document DT bindings and parse them in the TMU driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Document DT bindings and parse them in the CMT driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
The global spinlock is used to protect the shared start/stop register.
Now that all MTU2 channels are handled by a single device instance, use
a per-device spinlock.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The global spinlock is used to protect the shared start/stop register.
Now that all TMU channels are handled by a single device instance, use a
per-device spinlock.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
The global spinlock is used to protect the shared start/stop register.
Now that all CMT channels are handled by a single device instance, use a
per-device spinlock.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Move the clocksource Kconfig entries into their own menu, so that they
don't pollute the main device driver menu.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/20140616114845.343e9960@endymion.delvare
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
All Tegra SoCs have a freerunning microsecond counter which can be used as a
delay timer.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Unfortunately on some exynos systems, resetting the mct counter also
resets the architected timer counter. This can cause problems if the
architected timer driver has already been initialized because the kernel
will think that the counter has wrapped around, causing a big jump in
printk timestamps and delaying any scheduled clock events until the
counter reaches the value it had before it was reset.
The kernel code makes no assumptions about the initial value of the mct
counter so there is no reason from a software perspective to clear the
counter before starting it. This also fixes the problems described in
the previous paragraph.
Cc: Olof Johansson <olof@lixom.net>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Pull timer core updates from Thomas Gleixner:
"This time you get nothing really exciting:
- A huge update to the sh* clocksource drivers
- Support for two more ARM SoCs
- Removal of the deprecated setup_sched_clock() API
- The usual pile of fixlets all over the place"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
clocksource: Add Freescale FlexTimer Module (FTM) timer support
ARM: dts: vf610: Add Freescale FlexTimer Module timer node.
clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation
clocksource: sh_tmu: Remove unnecessary OOM messages
clocksource: sh_mtu2: Remove unnecessary OOM messages
clocksource: sh_cmt: Remove unnecessary OOM messages
clocksource: em_sti: Remove unnecessary OOM messages
clocksource: dw_apb_timer_of: Do not trace read_sched_clock
clocksource: Fix clocksource_mmio_readX_down
clocksource: Fix type confusion for clocksource_mmio_readX_Y
clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case
clocksource: qcom: Implement read_current_timer for udelay
ntp: Make is_error_status() use its argument
ntp: Convert simple_strtol to kstrtol
timer_stats/doc: Fix /proc/timer_stats documentation
sched_clock: Remove deprecated setup_sched_clock() API
ARM: sun6i: a31: Add support for the High Speed Timers
clocksource: sun5i: Add support for reset controller
clocksource: efm32: use $vendor,$device scheme for compatible string
KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform
...
- Another round of clean-up of FDT related code in architecture code.
This removes knowledge of internal FDT details from most architectures
except powerpc.
- Conversion of kernel's custom FDT parsing code to use libfdt.
- DT based initialization for generic serial earlycon. The introduction
of generic serial earlycon support went in thru tty tree.
- Improve the platform device naming for DT probed devices to ensure
unique naming and use parent names instead of a global index.
- Fix a race condition in of_update_property.
- Unify the various linker section OF match tables and fix several
function prototype errors.
- Update platform_get_irq_byname to work in deferred probe cases.
- 2 binding doc updates
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Merge tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next
Pull DeviceTree updates from Rob Herring:
- Another round of clean-up of FDT related code in architecture code.
This removes knowledge of internal FDT details from most
architectures except powerpc.
- Conversion of kernel's custom FDT parsing code to use libfdt.
- DT based initialization for generic serial earlycon. The
introduction of generic serial earlycon support went in through the
tty tree.
- Improve the platform device naming for DT probed devices to ensure
unique naming and use parent names instead of a global index.
- Fix a race condition in of_update_property.
- Unify the various linker section OF match tables and fix several
function prototype errors.
- Update platform_get_irq_byname to work in deferred probe cases.
- 2 binding doc updates
* tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (58 commits)
of: handle NULL node in next_child iterators
of/irq: provide more wrappers for !CONFIG_OF
devicetree: bindings: Document micrel vendor prefix
dt: bindings: dwc2: fix required value for the phy-names property
of_pci_irq: kill useless variable in of_irq_parse_pci()
of/irq: do irq resolution in platform_get_irq_byname()
of: Add a testcase for of_find_node_by_path()
of: Make of_find_node_by_path() handle /aliases
of: Create unlocked version of for_each_child_of_node()
lib: add glibc style strchrnul() variant
of: Handle memory@0 node on PPC32 only
pci/of: Remove dead code
of: fix race between search and remove in of_update_property()
of: Use NULL for pointers
of: Stop naming platform_device using dcr address
of: Ensure unique names without sacrificing determinism
tty/serial: pl011: add DT based earlycon support
of/fdt: add FDT serial scanning for earlycon
of/fdt: add FDT address translation support
serial: earlycon: add DT support
...
The newly merged versatile sched clock support uses a deprecated
interface. Of course that patch got routed through the ARM tree instead
of going through the relevant maintainer tree.
Use the proper interface so we can get rid of the cruft.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
SoC-near driver changes that we're merging through our tree. Mostly
because they depend on other changes we have staged, but in some cases
because the driver maintainers preferred that we did it this way.
This contains a largeish cleanup series of the omap_l3_noc bus driver,
cpuidle rework for Exynos, some reset driver conversions and a long
branch of TI EDMA fixes and cleanups, with more to come next release.
The TI EDMA cleanups is a shared branch with the dmaengine tree, with
a handful of Davinci-specific fixes on top.
After discussion at last year's KS (and some more on the mailing lists),
we are here adding a drivers/soc directory. The purpose of this is
to keep per-vendor shared code that's needed by different drivers but
that doesn't fit into the MFD (nor drivers/platform) model. We expect
to keep merging contents for this hierarchy through arm-soc so we can
keep an eye on what the vendors keep adding here and not making it a
free-for-all to shove in crazy stuff.
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Merge tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull ARM SoC driver changes from Olof Johansson:
"SoC-near driver changes that we're merging through our tree. Mostly
because they depend on other changes we have staged, but in some cases
because the driver maintainers preferred that we did it this way.
This contains a largeish cleanup series of the omap_l3_noc bus driver,
cpuidle rework for Exynos, some reset driver conversions and a long
branch of TI EDMA fixes and cleanups, with more to come next release.
The TI EDMA cleanups is a shared branch with the dmaengine tree, with
a handful of Davinci-specific fixes on top.
After discussion at last year's KS (and some more on the mailing
lists), we are here adding a drivers/soc directory. The purpose of
this is to keep per-vendor shared code that's needed by different
drivers but that doesn't fit into the MFD (nor drivers/platform)
model. We expect to keep merging contents for this hierarchy through
arm-soc so we can keep an eye on what the vendors keep adding here and
not making it a free-for-all to shove in crazy stuff"
* tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
tty: serial: msm: Remove direct access to GSBI
power: reset: keystone-reset: introduce keystone reset driver
Documentation: dt: add bindings for keystone pll control controller
Documentation: dt: add bindings for keystone reset driver
soc: qcom: fix of_device_id table
ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
ARM: EXYNOS: Move the driver to drivers/cpuidle directory
ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
ARM: EXYNOS: Pass the AFTR callback to the platform_data
ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
ARM: EXYNOS: Move the AFTR state function into pm.c
ARM: EXYNOS: Encapsulate the AFTR code into a function
ARM: EXYNOS: Disable cpuidle for exynos5440
ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
ARM: EXYNOS: Remove ifdef for scu_enable in pm
ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
ARM: EXYNOS: Use the cpu_pm notifier for pm
...
The bulk of this branch is updates for Renesas Shmobile. They are still
doing some enablement for classic boards first, and then come up with DT
bindings when they've had a chance to learn more about the hardware. Not
necessarily a bad way to go about it, and they're looking at moving some
of the temporary board code resulting from it to drivers/staging instead
to avoid the churn here.
As a result of the shmobile clock cleanups, we end up merging quite a
bit of SH code here as well. We ended up merging it here instead of in
the cleanup branch due to the other board changes depending on it.
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Merge tag 'boards-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull ARM SoC board support updates from Olof Johansson:
"The bulk of this branch is updates for Renesas Shmobile. They are
still doing some enablement for classic boards first, and then come up
with DT bindings when they've had a chance to learn more about the
hardware. Not necessarily a bad way to go about it, and they're
looking at moving some of the temporary board code resulting from it
to drivers/staging instead to avoid the churn here.
As a result of the shmobile clock cleanups, we end up merging quite a
bit of SH code here as well. We ended up merging it here instead of
in the cleanup branch due to the other board changes depending on it"
* tag 'boards-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (130 commits)
ARM: davinci: remove checks for CONFIG_USB_MUSB_PERIPHERAL
ARM: add drivers for Colibri T30 to multi_v7_defconfig
ARM: shmobile: Remove Genmai reference DTS
ARM: shmobile: Let Genmai multiplatform boot with Genmai DTB
ARM: shmobile: Sync Genmai DTS with Genmai reference DTS
ARM: shmobile: genmai-reference: Remove legacy clock support
ARM: shmobile: Remove non-multiplatform Genmai reference support
ARM: configs: enable XHCI mvebu support in multi_v7_defconfig
ARM: OMAP: replace checks for CONFIG_USB_GADGET_OMAP
ARM: OMAP: AM3517EVM: remove check for CONFIG_PANEL_SHARP_LQ043T1DG01
ARM: OMAP: SX1: remove check for CONFIG_SX1_OLD_FLASH
ARM: OMAP: remove some dead code
ARM: OMAP: omap3stalker: remove two Kconfig macros
ARM: tegra: tegra_defconfig updates
ARM: shmobile: r7s72100: use workaround for non DT-clocks
ARM: shmobile: Add forward declaration of struct clk to silence warning
ARM: shmobile: r7s72100: remove SPI DT clocks from legacy clock support
ARM: shmobile: r7s72100: add spi clocks to dtsi
ARM: shmobile: r7s72100: remove I2C DT clocks from legacy clock support
ARM: shmobile: r7s72100: add i2c clocks to dtsi
...
A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support for
big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation and
moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as most
of the other v7 platforms in the tree. \o/ The work isn't quite complete,
there's some driver fixes still needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
Plus a large set of various smaller updates for different platforms. I'm
probably missing some important one here.
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Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull part one of ARM SoC updates from Olof Johansson:
"A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support
for big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation
and moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as
most of the other v7 platforms in the tree. \o/
The work isn't quite complete, there's some driver fixes still
needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
plus a large set of various smaller updates for different platforms.
I'm probably missing some important one here"
* tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits)
ARM: exynos: don't run exynos4 l2x0 setup on other platforms
ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug
ARM: EXYNOS: mcpm rename the power_down_finish
ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC
ARM: EXYNOS: Enable multi-platform build support
ARM: EXYNOS: Consolidate Kconfig entries
ARM: EXYNOS: Add support for EXYNOS5410 SoC
ARM: EXYNOS: Support secondary CPU boot of Exynos3250
ARM: EXYNOS: Add Exynos3250 SoC ID
ARM: EXYNOS: Add 5800 SoC support
ARM: EXYNOS: initial board support for exynos5260 SoC
clk: exynos5410: register clocks using common clock framework
ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084
ARM: sunxi: allow building without reset controller
Documentation: devicetree: arm: sort enable-method entries
ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE
clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
ARM: dts: axxia: Add reset controller
power: reset: Add Axxia system reset driver
ARM: axxia: Adding defconfig for AXM55xx
...
Cleanups for 3.16. Among these are:
- A bunch of misc cleanups for Broadcom platforms, mostly housekeeping
- Enabling Common Clock Framework on the older s3c24xx Samsung chipsets
- Cleanup of the Versatile Express system controller code, moving it to syscon
- Power management cleanups for OMAP platforms
+ a handful of other cleanups across the place
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Merge tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull ARM SoC cleanups from Olof Johansson:
"Cleanups for 3.16. Among these are:
- a bunch of misc cleanups for Broadcom platforms, mostly
housekeeping
- enabling Common Clock Framework on the older s3c24xx Samsung
chipsets
- cleanup of the Versatile Express system controller code, moving it
to syscon
- power management cleanups for OMAP platforms
plus a handful of other cleanups across the place"
* tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
clk: samsung: fix build error
ARM: vexpress: refine dependencies for new code
clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares __initdata
cpufreq: exynos: Fix the compile error
ARM: S3C24XX: move debug-macro.S into the common space
ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
ARM: S3C24XX: trim down debug uart handling
ARM: compressed/head.S: remove s3c24xx special case
ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
ARM: EXYNOS: Remove exynos_subsys registration
ARM: EXYNOS: Remove duplicate lines in Makefile
ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
ARM: OMAP4: PRCM: remove references to cm-regbits-44xx.h from PRCM core files
ARM: OMAP3/4: PRM: add support of late_init call to prm_ll_ops
ARM: OMAP3/OMAP4: PRM: add prm_features flags and add IO wakeup under it
ARM: OMAP3/4: PRM: provide io chain reconfig function through irq setup
ARM: OMAP2+: PRM: remove unnecessary cpu_is_XXX calls from prm_init / exit
ARM: OMAP2+: PRCM: cleanup some header includes
...
- Add support for BIG Endian
- Add SOC_BUS support
- Sort Kconfig options
- Fix early console
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Merge tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx into next/soc
Merge "Xilinx Zynq changes for v3.16" from Michal Simek:
arm: Xilinx Zynq cleanup patches for v3.16
- Add support for BIG Endian
- Add SOC_BUS support
- Sort Kconfig options
- Fix early console
* tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: Enable big-endian
ARM: zynq: Fix uart0 early console virtual address
clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw
ARM: zynq: Sort Kconfig options
ARM: zynq: Add support for SOC_BUS
Signed-off-by: Olof Johansson <olof@lixom.net>
The versatile express changes for 3.16 introduced a number of
build regressions for randconfig kernels by not tracking dependencies
between the components right.
This patch tries to rectify that:
* the mach-vexpress code cannot link without the syscfg driver,
which in turn needs MFD_VEXPRESS_SYSREG
* various drivers call devm_regmap_init_vexpress_config(), which
has to be exported so it can be used by loadable modules
* the configuration bus uses OF DT helper functions that are not
available to platforms disable CONFIG_OF
* The sysreg driver exports GPIOs through gpiolib, which can
be disabled on some platforms.
* The clocksource code cannot be built on platforms that don't
use modern timekeeping but rely on gettimeoffset.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Freescale FlexTimer Module time reference is a 16-bit counter
that can be used as an unsigned or signed increase counter.
CNTIN defines the starting value of the count and MOD defines the
final value of the count. The value of CNTIN is loaded into the FTM
counter, and the counter increments until the value of MOD is reached,
at which point the counter is reloaded with the value of CNTIN. That's
also when an overflow interrupt will be generated.
Here using the 'evt' prefix or postfix as clock event device and
the 'src' as clock source device.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
We do not need to trace read_sched_clock function,
so add notrace attribute for this function.
Signed-off-by: Yang Wei <Wei.Yang@windriver.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
For some clocksource devices, for example, the registers are 32-bit, while
the lower 16-bit is used for timer counting(And reading the upper 16-bit
will return 0).
For example, when the counter value is 0x00001111, and then the
~readl_relaxed(to_mmio_clksrc(c)->reg) will return the value of 0xFFFFEEEE,
but it should be 0x0000EEEE.
So just using the c->mask to mask the unused bits.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The types' definations are:
o cycle_t -> u64
o readl_relaxed -> u32
o readw_relaxed -> u16
So let clocksource_mmio_readX_Ys return a cast to cycle_t, though
this maybe look reduntant sometimes, it make sense and they will be
more readable and less confusion...
This patch clarifies the functions type and fix it.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
tc_mode() can be called from interrupt context and thus must not call
clk_*prepare*() functions.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
irqchip will reject the affinity set to CPUs which is not online
yet. but in the CPU1 wakeup stage, OS only sets CPU1 to be online
after local timer is set, so that causes the irq_set_affinity not
work. this patch moves to irq_force_affinity() for the low level
boot stage.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
- register sched_clock callback to use clocksource mct-frc
Note that got ack from Daniel
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Merge tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
Merge "Samsung driver update for 3.16" from Kukjin Kim:
exynos_mct update for v3.16
- register sched_clock callback to use clocksource mct-frc
* tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
clocksource: exynos_mct: register sched_clock callback
Signed-off-by: Olof Johansson <olof@lixom.net>
This series reworks VE's platform configuration infrastructure by:
- making it possible to instantiate selected devices from the
Device Tree, prior to massive population,
- converting custom "func" API into standard "regmap",
- splitting the existing MFD driver into smaller ones and placing
them into relevant directories.
The common clock framework driver can now be selected individually
(mostly for arm64 sake, where some of them are not used at all).
It also simplifies the machine code, by:
- moving the shed clock info clocksource driver,
- simplifying SMP operations to base them entirely of the DT data,
- moving platform ID checks into relevant driver.
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Merge tag 'vexpress/updates-for-3.16' of git://git.linaro.org/people/pawel.moll/linux into next/cleanup
Merge "ARM Versatile Express updates for 3.16" from Pawel Moll:
This series reworks VE's platform configuration infrastructure by:
- making it possible to instantiate selected devices from the
Device Tree, prior to massive population,
- converting custom "func" API into standard "regmap",
- splitting the existing MFD driver into smaller ones and placing
them into relevant directories.
The common clock framework driver can now be selected individually
(mostly for arm64 sake, where some of them are not used at all).
It also simplifies the machine code, by:
- moving the shed clock info clocksource driver,
- simplifying SMP operations to base them entirely of the DT data,
- moving platform ID checks into relevant driver.
* tag 'vexpress/updates-for-3.16' of git://git.linaro.org/people/pawel.moll/linux:
ARM: vexpress: move HBI check to sysreg driver
ARM: vexpress: Simplify SMP operations for DT-powered system
ARM: vexpress: remove redundant vexpress_dt_cpus_num to get cpu count
clocksource: Sched clock source for Versatile Express
clk: versatile: Split config options for sp810 and vexpress_osc
mfd: vexpress: Define the device as MFD cells
mfd: syscon: Add platform data with a regmap config name
mfd: vexpress: Convert custom func API to regmap
of: Keep track of populated platform devices
+ Linux 3.15-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
Bringing in as an external dependency that the renesas/clock-cleanup2 branch
relies on.
* depends/clockevents-cleanups: (52 commits)
clocksource: sh_mtu2: Sort headers alphabetically
clocksource: sh_mtu2: Remove FSF mail address from GPL notice
clocksource: sh_mtu2: Rename clock to "fck" in the non-legacy case
clocksource: sh_mtu2: Add support for multiple channels per device
clocksource: sh_mtu2: Hardcode MTU2 clock event rating to 200
clocksource: sh_mtu2: Set cpumask to cpu_possible_mask
clocksource: sh_mtu2: Replace hardcoded register values with macros
clocksource: sh_mtu2: Allocate channels dynamically
clocksource: sh_mtu2: Replace kmalloc + memset with kzalloc
clocksource: sh_mtu2: Add index to struct sh_mtu2_channel
clocksource: sh_mtu2: Add memory base to sh_mtu2_channel structure
clocksource: sh_mtu2: Constify name argument to sh_mtu2_register()
clocksource: sh_mtu2: Split channel setup to separate function
clocksource: sh_mtu2: Rename struct sh_mtu2_priv to sh_mtu2_device
clocksource: sh_mtu2: Split channel fields from sh_mtu2_priv
clocksource: sh_mtu2: Turn sh_mtu2_priv fields into local variables
clocksource: sh_mtu2: Use request_irq() instead of setup_irq()
clocksource: sh_tmu: Sort headers alphabetically
clocksource: sh_tmu: Remove FSF mail address from GPL notice
clocksource: sh_tmu: Rename clock to "fck" in the non-legacy case
...
Signed-off-by: Olof Johansson <olof@lixom.net>
We now have several OF match tables using linker sections that are
nearly the same definition. The only variation is the callback function
prototype. Create a common define for creating linker section OF match
table entries which each table declaration can use.
Acked-by: Grant Likely <grant.likely@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
For supporting ARM big-endian is necessary to use
proper IO endianess accessors.
Based on Ben Dooks BE guide.
Similar conversion is done here:
"mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}"
(sha1: 5733c38ae3)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In the legacy platform data case each TMU platform device handles a
single channel with a single IRQ for the platform device. Retrieve the
IRQ using the logical channel number instead of the hardware channel
number.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Setup the same timer used as the clocksource to be used as the
read_current_timer implementation. This allows us to support a
stable udelay implementation on MSMs where it's possible for the
CPUs to scale speeds independently of one another.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch adds a trival sched clock source using free
running, 24MHz clocked counter present in the ARM Ltd.
reference platforms (Versatile, RealView, Versatile
Express) System Registers block.
This code replaces the call in the VE machine code.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Nobody want to know the connection between io clk and timer clk,
so exposing this information to timer module is not reasonable.
this patch moves to define the timers' clk in dt.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Use the clocksource mct-frc for sched_clock
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
clockevent fixes for 3.15 from Daniel Lezcano:
* Lorenzo Pieralizi fixed an issue with the arch_arm_timer where the
C3STOP flag for all the arch can cause some trouble by setting the
flag only if the power domain is not always on
* Alexander Shiyan fixed a compilation by changing the init function
to the right prototype
CC drivers/clocksource/zevio-timer.o
drivers/clocksource/zevio-timer.c:215:1: warning: comparison of distinct pointer types lacks a cast [enabled by default]
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
ARM arch timers are tightly coupled with the CPU logic and lose context
on platform implementing HW power management when cores are powered
down at run-time. Marking the arch timers as C3STOP regardless of power
management capabilities causes issues on platforms with no power management,
since in that case the arch timers cannot possibly enter states where the
timer loses context at runtime and therefore can always be used as a high
resolution clockevent device.
In order to fix the C3STOP issue in a way compliant with how real HW
works, this patch adds a boolean property to the arch timer bindings
to define if the arch timer is managed by an always-on power domain.
This power domain is present on all ARM platforms to date, and manages
HW that must not be turned off, whatever the state of other HW
components (eg power controller). On platforms with no power management
capabilities, it is the only power domain present, which encompasses
and manages power supply for all HW components in the system.
If the timer is powered by the always-on power domain, the always-on
property must be present in the bindings which means that the timer cannot
be shutdown at runtime, so it is not a C3STOP clockevent device.
If the timer binding does not contain the always-on property, the timer is
assumed to be power-gateable, hence it must be defined as a C3STOP
clockevent device.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Magnus Damm <damm@opensource.se>
Cc: Marc Carino <marc.ceeeee@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The Allwinner A31 that uses this timer has the timer IP asserted in reset.
Add an optional reset property to the DT, and deassert the timer from reset if
it's there.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch set cleans up the Renesas CMT and TMU drivers in preparation for DT
support.
The first 35 patches are a bunch of necessary cleanups that reorganize the CMT
and TMU drivers, their platform data, and the memory, interrupt and clock
resources they expect. As a result the drivers accept a new platform data
model close to the hardware with supports for all the timer channels using a
single device.
The next 13 patches (36/52 to 48/52) move all CMT and TMU platforms from the
old to the new platform data model. Patches 49/52 to 52/52 then drop support
for the old model and perform one more cleanup.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Wolfram Sang pointed out that "efm32,$device" is non-standard. So use the
common scheme and prefix device with "efm32-". The old compatible string
is left in place until arch/arm/boot/dts/efm32* is fixed.
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The check for a usable global timer in the probe code does not enquire
which CPU we are currently running on. This can cause the driver to
incorrectly assume we have an unusable global timer if we are running
on a CPU other than A9.
Before checking the CPU revision, ensure we are running on an A9 CPU.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
After hotplugging CPU1 the first call of interrupt handler for CPU1
oneshot timer was called on CPU0 because it fired before setting IRQ
affinity. Affected are SoCs where Multi Core Timer interrupts are
shared (SPI), e.g. Exynos 4210.
During setup of the MCT timers the clock event device should be
registered after setting the affinity for interrupt. This will prevent
starting the timer too early.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>,
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org,
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20140416143316.299247848@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The starting cpu is not yet in the online mask so irq_set_affinity()
fails which results in per cpu timers for this cpu ending up on some
other online cpu, ususally cpu 0.
Use irq_force_affinity() which disables the online mask check and
makes things work.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>,
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org,
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20140416143316.106665251@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This helps locating duplicates and inserting new headers.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already
includes a copy of the GPL.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The sh_mtu2 driver gets the MTU2 functional clock using a connection ID
of "mtu2_fck". While all SH SoCs create clock lookup entries with a NULL
device ID and a "mtu2_fck" connection ID, the ARM SoCs use the device ID
only with a NULL connection ID. This works on legacy platforms but will
break on ARM with DT boot.
Fix the situation by using a connection ID of "fck" in the non-legacy
platform data case. Clock lookup entries will be renamed to use the
device ID as well as the connection ID as platforms get moved to new
platform data. The legacy code will eventually be dropped, leaving us
with device ID based clock lookup, compatible with DT boot.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
MTU2 hardware devices can support multiple channels, with global
registers and per-channel registers. The sh_mtu2 driver currently models
the hardware with one Linux device per channel. This model makes it
difficult to handle global registers in a clean way.
Add support for a new model that uses one Linux device per timer with
multiple channels per device. This requires changes to platform data,
add new channel configuration fields.
Support for the legacy model is kept and will be removed after all
platforms switch to the new model.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
All boards use clock event ratings of 200 for the MTU2, hardcode it in
the driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The MTU2 is not tied to CPU0, make it usable on any CPU.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Define symbolic macros for all used registers bits.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
This prepares the driver for multi-channel support.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
One kzalloc a day keeps the bugs away.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Use the index as the timer start/stop bit and when printing messages to
identify the channel.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The channel memory base is channel-specific, add it to the channel
structure in preparation for support of multiple channels per device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The name argument is assigned to const structure fields only, constify
it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Move the channel setup code from sh_mtu2_setup to a new
sh_mtu2_setup_channel function and call it from sh_mtu2_setup.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Channel data is private as well, rename priv to device to make the
distrinction between the core device and the channels clearer.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Create a new sh_mtu2_channel structure to hold the channel-specific
fields in preparation for multiple channels per device support.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The rate and periodic fields are used in a single function only, as
local variables. Remove them from the structure.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
The driver claims it needs to register an interrupt handler too early
for request_irq(). This might have been true in the past, but the only
meaningful difference between request_irq() and setup_irq() today is an
additional kzalloc() call in request_irq(). As the driver calls
kmalloc() itself we know that the slab allocator is available, we can
thus switch to request_irq().
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already
includes a copy of the GPL.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The sh_tmu driver gets the TMU functional clock using a connection ID of
"tmu_fck". While all SH SoCs create clock lookup entries with a NULL
device ID and a "tmu_fck" connection ID, the ARM SoCs use the device ID
only with a NULL connection ID. This works on legacy platforms but will
break on ARM with DT boot.
Fix the situation by using a connection ID of "fck" in the non-legacy
platform data case. Clock lookup entries will be renamed to use the
device ID as well as the connection ID as platforms get moved to new
platform data. The legacy code will eventually be dropped, leaving us
with device ID based clock lookup, compatible with DT boot.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
TMU hardware devices can support multiple channels, with global
registers and per-channel registers. The sh_tmu driver currently models
the hardware with one Linux device per channel. This model makes it
difficult to handle global registers in a clean way.
Add support for a new model that uses one Linux device per timer with
multiple channels per device. This requires changes to platform data,
add new channel configuration fields.
Support for the legacy model is kept and will be removed after all
platforms switch to the new model.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All boards use clock event and clock source ratings of 200 for the TMU,
hardcode it in the driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Use the index as the timer start/stop bit and when printing messages to
identify the channel.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The channel memory base is channel-specific, add it to the channel
structure in preparation for support of multiple channels per device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Move the channel setup code from sh_tmu_setup to a new
sh_tmu_setup_channel function and call it from sh_tmu_setup.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Channel data is private as well, rename priv to device to make the
distrinction between the core device and the channels clearer.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Create a new sh_tmu_channel structure to hold the channel-specific
field in preparation for multiple channels per device support.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The driver claims it needs to register an interrupt handler too early
for request_irq(). This might have been true in the past, but the only
meaningful difference between request_irq() and setup_irq() today is an
additional kzalloc() call in request_irq(). As the driver calls
kmalloc() itself we know that the slab allocator is available, we can
thus switch to request_irq().
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Clock sources don't need an IRQ, request the IRQ only for channels used
as clock event devices.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already
includes a copy of the GPL.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The sh_cmt driver gets the CMT functional clock using a connection ID of
"cmt_fck". While all SH SoCs create clock lookup entries with a NULL
device ID and a "cmt_fck" connection ID, the ARM SoCs use the device ID
only with a NULL connection ID. This works on legacy platforms but will
break on ARM with DT boot.
Fix the situation by using a connection ID of "fck" in the non-legacy
platform data case. Clock lookup entries will be renamed to use the
device ID as well as the connection ID as platforms get moved to new
platform data. The legacy code will eventually be dropped, leaving us
with device ID based clock lookup, compatible with DT boot.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
CMT hardware devices can support multiple channels, with global
registers and per-channel registers. The sh_cmt driver currently models
the hardware with one Linux device per channel. This model makes it
difficult to handle global registers in a clean way.
Add support for a new model that uses one Linux device per timer with
multiple channels per device. This requires changes to platform data,
add new channel configuration fields.
Support for the legacy model is kept and will be removed after all
platforms switch to the new model.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All boards use or should use a clock source rating of 125 for the CMT,
hardcode it in the driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All boards use or should use a clock event rating of 125 for the CMT,
hardcode it in the driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The CMT is a global timer not restricted to a single CPU. It has a lower
rating than the TMU or ARM architected timer, but is still useful on
systems where the other timers are stopped during CPU sleep.
When multiple timers are available the timers core selects which timer
to use based on timer ratings.
On SMP systems where timer broadcasting is required, one dummy timer is
instantiated per CPU with a rating of 100. On those systems the CMT
timer has a rating of 80, which makes the dummy timer selected by
default on all CPUs. The CMT is then available, and will be used as a
broadcast timer.
On UP systems no dummy timer is instantiated. The CMT timer has a rating
of 125 on those systems and is used directly as a clock event device for
CPU0 without broadcasting.
The CMT rating shouldn't depend on whether we boot a UP or SMP system.
We can't raise the CMT rating to 125 on SMP systems. This would select
CMT as the clock event device for CPU0 as its rating is higher than the
dummy timer rating, and would leave the system without a broadcast
timer. We could instead lower the rating to 80 on all systems, but that
wouldn't reflect reality as ratings between 1 and 99 are documented as
"unfit for real use".
We should raise the rating above 99 and still have the CMT selected as a
broadcast timer. This can be done by changing the cpumask from
cpumask_of(0) to cpu_possible_mask. In that case the timer selection
logic will prefer the previously probed and already selected dummy timer
for all CPUs based on the fact that already selected per-cpu timers are
preferred over new global timers, regardless of their respective
ratings. This also better reflects reality, as the CMT is not tied to
the boot CPU.
Ideally the timer selection logic should realize that the CMT needs to
be used as a broadcast timer on SMP systems as no other broadcast timer
is available, regardless of the cpumask and rating.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Create a new sh_cmt_info structure to hold static information about the
device model and reference that structure from the sh_cmt_device
structure.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The channel memory base is channel-specific, add it to the channel
structure in preparation for support of multiple channels per device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The mapbase variable points to the mapped base address of the channel,
rename it to mapbase_sh. mapbase_str points to the mapped base address
of the CMT device, rename it to mapbase.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Move the channel setup code from sh_cmt_setup to a new
sh_cmt_setup_channel function and call it from sh_cmt_setup.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Channel data is private as well, rename priv to device to make the
distrinction between the core device and the channels clearer.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Create a new sh_cmt_channel structure to hold the channel-specific
field in preparation for multiple channels per device support.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The driver claims it needs to register an interrupt handler too early
for request_irq(). This might have been true in the past, but the only
meaningful difference between request_irq() and setup_irq() today is an
additional kzalloc() call in request_irq(). As the driver calls
kmalloc() itself we know that the slab allocator is available, we can
thus switch to request_irq().
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The purpose of this single series of commits from Srivatsa S Bhat (with
a small piece from Gautham R Shenoy) touching multiple subsystems that use
CPU hotplug notifiers is to provide a way to register them that will not
lead to deadlocks with CPU online/offline operations as described in the
changelog of commit 93ae4f978c (CPU hotplug: Provide lockless versions
of callback registration functions).
The first three commits in the series introduce the API and document it
and the rest simply goes through the users of CPU hotplug notifiers and
converts them to using the new method.
/
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Merge tag 'cpu-hotplug-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull CPU hotplug notifiers registration fixes from Rafael Wysocki:
"The purpose of this single series of commits from Srivatsa S Bhat
(with a small piece from Gautham R Shenoy) touching multiple
subsystems that use CPU hotplug notifiers is to provide a way to
register them that will not lead to deadlocks with CPU online/offline
operations as described in the changelog of commit 93ae4f978c ("CPU
hotplug: Provide lockless versions of callback registration
functions").
The first three commits in the series introduce the API and document
it and the rest simply goes through the users of CPU hotplug notifiers
and converts them to using the new method"
* tag 'cpu-hotplug-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (52 commits)
net/iucv/iucv.c: Fix CPU hotplug callback registration
net/core/flow.c: Fix CPU hotplug callback registration
mm, zswap: Fix CPU hotplug callback registration
mm, vmstat: Fix CPU hotplug callback registration
profile: Fix CPU hotplug callback registration
trace, ring-buffer: Fix CPU hotplug callback registration
xen, balloon: Fix CPU hotplug callback registration
hwmon, via-cputemp: Fix CPU hotplug callback registration
hwmon, coretemp: Fix CPU hotplug callback registration
thermal, x86-pkg-temp: Fix CPU hotplug callback registration
octeon, watchdog: Fix CPU hotplug callback registration
oprofile, nmi-timer: Fix CPU hotplug callback registration
intel-idle: Fix CPU hotplug callback registration
clocksource, dummy-timer: Fix CPU hotplug callback registration
drivers/base/topology.c: Fix CPU hotplug callback registration
acpi-cpufreq: Fix CPU hotplug callback registration
zsmalloc: Fix CPU hotplug callback registration
scsi, fcoe: Fix CPU hotplug callback registration
scsi, bnx2fc: Fix CPU hotplug callback registration
scsi, bnx2i: Fix CPU hotplug callback registration
...
These cleanup patches are mainly move stuff around and should all
be harmless. They are mainly split out so that other branches can
be based on top to avoid conflicts.
Notable changes are:
* We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
longer used. (Uwe Kleine-König)
* The Qualcomm MSM platform is split out into legacy mach-msm and
new-style mach-qcom, to allow easier maintainance of the new
hardware support without regressions. (Kumar Gala)
* A rework of some of the Kconfig logic to simplify multiplatform
support (Rob Herring)
* Samsung Exynos gets closer to supporting multiplatform (Sachin
Kamat and others)
* mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
* at91 gains some common clock framework support (Alexandre Belloni,
Jean-Jacques Hiblot and other French people).
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Merge tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann:
"These cleanup patches are mainly move stuff around and should all be
harmless. They are mainly split out so that other branches can be
based on top to avoid conflicts.
Notable changes are:
- We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
longer used (Uwe Kleine-König)
- The Qualcomm MSM platform is split out into legacy mach-msm and
new-style mach-qcom, to allow easier maintainance of the new
hardware support without regressions (Kumar Gala)
- A rework of some of the Kconfig logic to simplify multiplatform
support (Rob Herring)
- Samsung Exynos gets closer to supporting multiplatform (Sachin
Kamat and others)
- mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
- at91 gains some common clock framework support (Alexandre Belloni,
Jean-Jacques Hiblot and other French people)"
* tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits)
ARM: hisi: select HAVE_ARM_SCU only for SMP
ARM: efm32: allow uncompress debug output
ARM: prima2: build reset code standalone
ARM: at91: add PWM clock
ARM: at91: move sam9261 SoC to common clk
ARM: at91: prepare common clk transition for sam9261 SoC
ARM: at91: updated the at91_dt_defconfig with support for the ADS7846
ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek
ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs
ARM: at91: dt: Add at91sam9261 dt SoC support
ARM: at91: switch sam9rl to common clock framework
ARM: at91/dt: define main clk frequency of at91sam9rlek
ARM: at91/dt: define at91sam9rl clocks
ARM: at91: prepare common clk transition for sam9rl SoCs
ARM: at91: prepare sam9 dt boards transition to common clk
ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek
ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs
ARM: at91: Add at91sam9rl DT SoC support
ARM: at91: prepare at91sam9rl DT transition
ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig
...
Pull ARM changes from Russell King:
- Perf updates from Will Deacon:
- Support for Qualcomm Krait processors (run perf on your phone!)
- Support for Cortex-A12 (run perf stat on your FPGA!)
- Support for perf_sample_event_took, allowing us to automatically decrease
the sample rate if we can't handle the PMU interrupts quickly enough
(run perf record on your FPGA!).
- Basic uprobes support from David Long:
This patch series adds basic uprobes support to ARM. It is based on
patches developed earlier by Rabin Vincent. That approach of adding
hooks into the kprobes instruction parsing code was not well received.
This approach separates the ARM instruction parsing code in kprobes out
into a separate set of functions which can be used by both kprobes and
uprobes. Both kprobes and uprobes then provide their own semantic action
tables to process the results of the parsing.
- ARMv7M (microcontroller) updates from Uwe Kleine-König
- OMAP DMA updates (recently added Vinod's Ack even though they've been
sitting in linux-next for a few months) to reduce the reliance of
omap-dma on the code in arch/arm.
- SA11x0 changes from Dmitry Eremin-Solenikov and Alexander Shiyan
- Support for Cortex-A12 CPU
- Align support for ARMv6 with ARMv7 so they can cooperate better in a
single zImage.
- Addition of first AT_HWCAP2 feature bits for ARMv8 crypto support.
- Removal of IRQ_DISABLED from various ARM files
- Improved efficiency of virt_to_page() for single zImage
- Patch from Ulf Hansson to permit runtime PM callbacks to be available for
AMBA devices for suspend/resume as well.
- Finally kill asm/system.h on ARM.
* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (89 commits)
dmaengine: omap-dma: more consolidation of CCR register setup
dmaengine: omap-dma: move IRQ handling to omap-dma
dmaengine: omap-dma: move register read/writes into omap-dma.c
ARM: omap: dma: get rid of 'p' allocation and clean up
ARM: omap: move dma channel allocation into plat-omap code
ARM: omap: dma: get rid of errata global
ARM: omap: clean up DMA register accesses
ARM: omap: remove almost-const variables
ARM: omap: remove references to disable_irq_lch
dmaengine: omap-dma: cleanup errata 3.3 handling
dmaengine: omap-dma: provide register read/write functions
dmaengine: omap-dma: use cached CCR value when enabling DMA
dmaengine: omap-dma: move barrier to omap_dma_start_desc()
dmaengine: omap-dma: move clnk_ctrl setting to preparation functions
dmaengine: omap-dma: improve efficiency loading C.SA/C.EI/C.FI registers
dmaengine: omap-dma: consolidate clearing channel status register
dmaengine: omap-dma: move CCR buffering disable errata out of the fast path
dmaengine: omap-dma: provide register definitions
dmaengine: omap-dma: consolidate setup of CCR
dmaengine: omap-dma: consolidate setup of CSDP
...
Pull x86 old platform removal from Peter Anvin:
"This patchset removes support for several completely obsolete
platforms, where the maintainers either have completely vanished or
acked the removal. For some of them it is questionable if there even
exists functional specimens of the hardware"
Geert Uytterhoeven apparently thought this was a April Fool's pull request ;)
* 'x86-nuke-platforms-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86, platforms: Remove NUMAQ
x86, platforms: Remove SGI Visual Workstation
x86, apic: Remove support for IBM Summit/EXA chipset
x86, apic: Remove support for ia32-based Unisys ES7000
Pull timer changes from Thomas Gleixner:
"This assorted collection provides:
- A new timer based timer broadcast feature for systems which do not
provide a global accessible timer device. That allows those
systems to put CPUs into deep idle states where the per cpu timer
device stops.
- A few NOHZ_FULL related improvements to the timer wheel
- The usual updates to timer devices found in ARM SoCs
- Small improvements and updates all over the place"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
tick: Remove code duplication in tick_handle_periodic()
tick: Fix spelling mistake in tick_handle_periodic()
x86: hpet: Use proper destructor for delayed work
workqueue: Provide destroy_delayed_work_on_stack()
clocksource: CMT, MTU2, TMU and STI should depend on GENERIC_CLOCKEVENTS
timer: Remove code redundancy while calling get_nohz_timer_target()
hrtimer: Rearrange comments in the order struct members are declared
timer: Use variable head instead of &work_list in __run_timers()
clocksource: exynos_mct: silence a static checker warning
arm: zynq: Add support for cpufreq
arm: zynq: Don't use arm_global_timer with cpufreq
clocksource/cadence_ttc: Overhaul clocksource frequency adjustment
clocksource/cadence_ttc: Call clockevents_update_freq() with IRQs enabled
clocksource: Add Kconfig entries for CMT, MTU2, TMU and STI
sh: Remove Kconfig entries for TMU, CMT and MTU2
ARM: shmobile: Remove CMT, TMU and STI Kconfig entries
clocksource: armada-370-xp: Use atomic access for shared registers
clocksource: orion: Use atomic access for shared registers
clocksource: timer-keystone: Delete unnecessary variable
clocksource: timer-keystone: introduce clocksource driver for Keystone
...
If GENERIC_CLOCKEVENTS=n:
drivers/clocksource/sh_cmt.c:54:28: error: field 'ced' has incomplete type
drivers/clocksource/sh_cmt.c: In function 'sh_cmt_interrupt':
drivers/clocksource/sh_cmt.c:407:23: error: 'CLOCK_EVT_MODE_ONESHOT' undeclared (first use in this function)
drivers/clocksource/sh_mtu2.c:44:28: error: field 'ced' has incomplete type
drivers/clocksource/sh_mtu2.c: In function 'ced_to_sh_mtu2':
drivers/clocksource/sh_mtu2.c:184:70: warning: initialization from incompatible pointer type [enabled by default]
drivers/clocksource/sh_mtu2.c: At top level:
drivers/clocksource/sh_mtu2.c:188:16: warning: 'enum clock_event_mode' declared inside parameter list [enabled by default]
drivers/clocksource/sh_tmu.c:45:28: error: field 'ced' has incomplete type
drivers/clocksource/sh_tmu.c: In function 'sh_tmu_interrupt':
drivers/clocksource/sh_tmu.c:207:21: error: 'CLOCK_EVT_MODE_ONESHOT' undeclared (first use in this function)
drivers/clocksource/em_sti.c:44:28: error: field 'ced' has incomplete type
drivers/clocksource/em_sti.c: In function 'ced_to_em_sti':
drivers/clocksource/em_sti.c:251:69: warning: initialization from incompatible pointer type [enabled by default]
drivers/clocksource/em_sti.c: At top level:
drivers/clocksource/em_sti.c:255:16: warning: 'enum clock_event_mode' declared inside parameter list [enabled by default]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Magnus Damm <damm@opensource.se>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/1395324352-9146-1-git-send-email-geert@linux-m68k.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Subsystems that want to register CPU hotplug callbacks, as well as perform
initialization for the CPUs that are already online, often do it as shown
below:
get_online_cpus();
for_each_online_cpu(cpu)
init_cpu(cpu);
register_cpu_notifier(&foobar_cpu_notifier);
put_online_cpus();
This is wrong, since it is prone to ABBA deadlocks involving the
cpu_add_remove_lock and the cpu_hotplug.lock (when running concurrently
with CPU hotplug operations).
Instead, the correct and race-free way of performing the callback
registration is:
cpu_notifier_register_begin();
for_each_online_cpu(cpu)
init_cpu(cpu);
/* Note the use of the double underscored version of the API */
__register_cpu_notifier(&foobar_cpu_notifier);
cpu_notifier_register_done();
Fix the clocksource dummy-timer code by using this latter form of callback
registration.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
My guess is we aren't going to have a 2 digit cpuid here any time soon
but the static checkers don't know that and complain that the snprintf()
could overflow.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The currently used method adjusting the clocksource to a changing input
frequency does not work on kernels from 3.11 on.
The new approach is to keep the timer frequency as constant as possible.
I.e.
- due to the TTC's prescaler limitations, allow frequency changes
only if the frequency scales by a power of 2
- adjust the counter's divider on the fly when a frequency change
occurs
This limits cpufreq to scale by certain factors only.
But we may keep the time base somewhat constant, so that sleep() & co
keep working as expected, while supporting cpufreq.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
The timer core takes care of serialization and IRQs. Hence the driver is
no longer required to disable interrupts when calling
clockevents_update_freq().
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Add Kconfig entries for CMT, MTU2, TMU and STI to
drivers/clocksource/Kconfig. This will allow us to
get rid of duplicated entires in architecture code
such as arch/sh and arch/arm/mach-shmobile.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Replace the driver-specific thread-safe shared register API
by the recently introduced atomic_io_clear_set().
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Replace the driver-specific thread-safe shared register API
by the recently introduced atomic_io_clear_set().
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Commit 438e0bff5257 added the timer-keystone device driver but make use
of an unnecessary variable in the init function. This patch deletes this
variable.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Add broadcast clock-event device for the Keystone arch.
The timer can be configured as a general-purpose 64-bit timer,
dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or
independently (unchained mode) of each other.
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Santosh shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The Allwinner A10 compatibles were following a slightly different compatible
patterns than the rest of the SoCs for historical reasons. Add compatibles
matching the other pattern to the timer driver for consistency, and keep the
older one for backward compatibility.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Move the U300 timer driver down to the clocksource driver
subsystem and keep arch/arm clean.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Set the CLOCK_EVT_FEAT_DYNIRQ flag on the memory mapped
clockevent so that we save power by waking up the CPU with the
next event when this timer is used in broadcast mode.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Split of the multiplatform support for the Qualcomm SoCs into a mach-qcom
while we leave mach-msm as legacy support. Also, some smp and device tree
related cleanups.
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Merge tag 'qcom-cleanup-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/cleanup
Merge "General cleanups for MSM/QCOM for 3.15" from Kumar Gala:
Split of the multiplatform support for the Qualcomm SoCs into a mach-qcom
while we leave mach-msm as legacy support. Also, some smp and device tree
related cleanups.
* tag 'qcom-cleanup-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
ARM: qcom: Rename various msm prefixed functions to qcom
clocksource: qcom: split building of legacy vs multiplatform support
ARM: qcom: Split Qualcomm support into legacy and multiplatform
clocksource: qcom: Move clocksource code out of mach-msm
ARM: msm: kill off hotplug.c
ARM: msm: Remove pen_release usage
ARM: dts: msm: split out msm8660 and msm8960 soc into dts include
Signed-off-by: Olof Johansson <olof@lixom.net>
ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since
387798b (ARM: initial multiplatform support).)
To make this work some code out of arch/arm needed to be adapted. The
respective changes got acks by their maintainers to be taken via armsoc
(with Andrew Morton substituting for Alessandro Zummo as rtc maintainer).
Compared to the previous pull request there was another patch added that
fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not
squash this fix into the original commit to save him from the need to
reverify the series.
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Merge tag 'dropmachtimexh-v2' of git://git.pengutronix.de/git/ukl/linux into next/cleanup
This cleanup series gets rid of <mach/timex.h> for platforms not using
ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since
387798b (ARM: initial multiplatform support).)
To make this work some code out of arch/arm needed to be adapted. The
respective changes got acks by their maintainers to be taken via armsoc
(with Andrew Morton substituting for Alessandro Zummo as rtc maintainer).
Compared to the previous pull request there was another patch added that
fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not
squash this fix into the original commit to save him from the need to
reverify the series.
* tag 'dropmachtimexh-v2' of git://git.pengutronix.de/git/ukl/linux:
ARM: ixp4xx: fix timer latch calculation
ARM: drop <mach/timex.h> for !ARCH_MULTIPLATFORM, too
ARM: rpc: stop using <mach/timex.h>
ARM: ixp4xx: stop using <mach/timex.h>
input: ixp4xx-beeper: don't use symbols from <mach/timex.h>
ARM: at91: don't use <mach/timex.h>
ARM: ep93xx: stop using mach/timex.h
ARM: mmp: stop using mach/timex.h
ARM: netx: stop using mach/timex.h
ARM: sa1100: stop using mach/timex.h
clocksource: sirf/marco+prima2: drop usage of CLOCK_TICK_RATE
rtc: pxa: drop unused #define TIMER_FREQ
rtc: at91sam9: include <mach/hardware.h> explicitly
ARM/serial: at91: switch atmel serial to use gpiolib
Signed-off-by: Olof Johansson <olof@lixom.net>
There should no longer be any IBM x440 systems or those using the
Summit/EXA chipset out in the wild, so remove support for it.
We've done our due diligence in reaching out to any contact information
listed for this chipset and no indication was given that it should be
kept around.
Signed-off-by: David Rientjes <rientjes@google.com>
The majority of the clocksource code for the Qualcomm platform is shared
between newer (multiplatform) and older platforms. However there is a bit
of code that isn't, so only build it for the appropriate config.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Since there may be other clocksources available, this driver should not
trigger a panic simply because it can not determine the frequency of an
external clock. This change refactors the driver to allow a warning to
be printed in this case instead.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Cc: Christian Daudt <bcm@fixthebug.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/1391559304-26558-1-git-send-email-tim.kryger@linaro.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
We intend to share the clocksource code for MSM platforms between legacy
and multiplatform supported qcom SoCs.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
When an clock is specified in the device tree, enable it and use it to
determine the external clock frequency.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Christian Daudt <bcm@fixthebug.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
DT and DT-conversion-related changes for various ARM platforms. Most
of these are to enable various devices on various boards, etc, and not
necessarily worth enumerating.
New boards and systems continue to come in as new devicetree files that
don't require corresponding C changes any more, which is indicating that
the system is starting to work fairly well.
A few things worth pointing out:
* ST Ericsson ux500 platforms have made the major push to move over to fully
support the platform with DT.
* Renesas platforms continue their conversion over from legacy platform devices
to DT-based for hardware description.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"DT and DT-conversion-related changes for various ARM platforms. Most
of these are to enable various devices on various boards, etc, and not
necessarily worth enumerating.
New boards and systems continue to come in as new devicetree files
that don't require corresponding C changes any more, which is
indicating that the system is starting to work fairly well.
A few things worth pointing out:
* ST Ericsson ux500 platforms have made the major push to move over
to fully support the platform with DT
* Renesas platforms continue their conversion over from legacy
platform devices to DT-based for hardware description"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits)
ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync
ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6
ARM: dts: sirf: add lost minigpsrtc device node
ARM: dts: sirf: add clock, frequence-voltage table for CPU0
ARM: dts: sirf: add lost bus_width, clock and status for sdhci
ARM: dts: sirf: add lost clocks for cphifbg
ARM: dts: socfpga: add pl330 clock
ARM: dts: socfpga: update L2 tag and data latency
arm: sun7i: cubietruck: Enable the i2c controllers
ARM: dts: add support for EXYNOS4412 based TINY4412 board
ARM: dts: Add initial support for Arndale Octa board
ARM: bcm2835: add USB controller to device tree
ARM: dts: MSM8974: Add MMIO architected timer node
ARM: dts: MSM8974: Add restart node
ARM: dts: sun7i: external clock outputs
ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style
ARM: dts: sun7i: Add pin muxing options for clock outputs
ARM: dts: sun7i: Add rtp controller node
ARM: dts: sun5i: Add rtp controller node
ARM: dts: sun4i: Add rtp controller node
...
New core SoC-specific changes.
New platforms:
* Introduction of a vendor, Hisilicon, and one of their SoCs with some
random numerical product name.
* Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m, i.e. !MMU).
* Marvell Berlin series of SoCs, which include the one in Chromecast.
* MOXA platform support, ARM9-based platform used mostly in industrial products
* Support for Freescale's i.MX50 SoC.
Other work:
* Renesas work for new platforms and drivers, and conversion over to
more multiplatform-friendly device registration schemes.
* SMP support for Allwinner sunxi platforms.
* ... plus a bunch of other stuff across various platforms.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"New core SoC-specific changes.
New platforms:
* Introduction of a vendor, Hisilicon, and one of their SoCs with
some random numerical product name.
* Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
i.e. !MMU).
* Marvell Berlin series of SoCs, which include the one in Chromecast.
* MOXA platform support, ARM9-based platform used mostly in
industrial products
* Support for Freescale's i.MX50 SoC.
Other work:
* Renesas work for new platforms and drivers, and conversion over to
more multiplatform-friendly device registration schemes.
* SMP support for Allwinner sunxi platforms.
* ... plus a bunch of other stuff across various platforms"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
ARM: tegra: fix tegra_powergate_sequence_power_up() inline
ARM: msm_defconfig: Update for multi-platform
ARM: msm: Move MSM's DT based hardware to multi-platform support
ARM: msm: Only build timer.c if required
ARM: msm: Only build clock.c on proc_comm based platforms
ARM: ux500: Enable system suspend with WFI support
ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
ARM: shmobile: r8a7790: Fix I2C controller names
ARM: msm: Simplify ARCH_MSM_DT config
ARM: msm: Add support for MSM8974 SoC
ARM: sunxi: select ARM_PSCI
MAINTAINERS: Update Allwinner sunXi maintainer files
ARM: sunxi: Select RESET_CONTROLLER
ARM: imx: improve the comment of CCM lpm SW workaround
ARM: imx: improve status check of clock gate
ARM: imx: add necessary interface for pfd
ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
ARM: imx: Add cpu frequency scaling support
ARM i.MX35: Add devicetree support.
...
The 32-bit sched_clock() interface supports 64 bits since
3.13-rc1. Upgrade to the 64-bit function to allow us to remove
the 32-bit registration interface.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1389922686-6249-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Pull clocksource/clockevent updates from Daniel Lezcano:
* Axel Lin removed an unused structure defining the ids for the
bcm kona driver.
* Ezequiel Garcia enabled the timer divider only when the 25MHz
timer is not used for the armada 370 XP.
* Jingoo Han removed a pointless platform data initialization for
the sh_mtu and sh_mtu2.
* Laurent Pinchart added the clk_prepare/clk_unprepare for sh_cmt.
* Linus Walleij added a useful warning in clk_of when no clocks
are found while the old behavior was to silently hang at boot time.
* Maxime Ripard added the high speed timer drivers for the
Allwinner SoCs (A10, A13, A20). He increased the rating, shared the
irq across all available cpus and fixed the clockevent's irq
initialization for the sun4i.
* Michael Opdenacker removed the usage of the IRQF_DISABLED for the
all the timers driver located in drivers/clocksource.
* Stephen Boyd switched to sched_clock_register for the
arm_global_timer, cadence_ttc, sun4i and orion timers.
Conflicts:
drivers/clocksource/clksrc-of.c
Signed-off-by: Ingo Molnar <mingo@kernel.org>
When the kernel is compiled with:
CONFIG_HIGH_RES_TIMERS=no
CONFIG_HZ_PERIODIC=yes
CONFIG_DEBUG_ATOMIC_SLEEP=yes
The following WARN appears:
WARNING: CPU: 1 PID: 0 at linux/kernel/mutex.c:856 mutex_trylock+0x70/0x1fc()
DEBUG_LOCKS_WARN_ON(in_interrupt())
Modules linked in:
CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.12.0-xilinx-dirty #93
[<c0014a78>] (unwind_backtrace+0x0/0x11c) from [<c0011b6c>] (show_stack+0x10/0x14)
[<c0011b6c>] (show_stack+0x10/0x14) from [<c039120c>] (dump_stack+0x7c/0xc0)
[<c039120c>] (dump_stack+0x7c/0xc0) from [<c001fda4>] (warn_slowpath_common+0x60/0x84)
[<c001fda4>] (warn_slowpath_common+0x60/0x84) from [<c001fe48>] (warn_slowpath_fmt+0x2c/0x3c)
[<c001fe48>] (warn_slowpath_fmt+0x2c/0x3c) from [<c0392658>] (mutex_trylock+0x70/0x1fc)
[<c0392658>] (mutex_trylock+0x70/0x1fc) from [<c02dfc08>] (clk_prepare_lock+0xc/0xe4)
[<c02dfc08>] (clk_prepare_lock+0xc/0xe4) from [<c02e099c>] (clk_get_rate+0xc/0x44)
[<c02e099c>] (clk_get_rate+0xc/0x44) from [<c02d0394>] (ttc_set_mode+0x34/0x78)
[<c02d0394>] (ttc_set_mode+0x34/0x78) from [<c005f794>] (clockevents_set_mode+0x28/0x5c)
[<c005f794>] (clockevents_set_mode+0x28/0x5c) from [<c00607fc>] (tick_broadcast_on_off+0x190/0x1c0)
[<c00607fc>] (tick_broadcast_on_off+0x190/0x1c0) from [<c005f168>] (clockevents_notify+0x58/0x1ac)
[<c005f168>] (clockevents_notify+0x58/0x1ac) from [<c02b99dc>] (cpuidle_setup_broadcast_timer+0x20/0x24)
[<c02b99dc>] (cpuidle_setup_broadcast_timer+0x20/0x24) from [<c006cd04>] (generic_smp_call_function_single_interrupt+0)
[<c006cd04>] (generic_smp_call_function_single_interrupt+0xe0/0x130) from [<c00138c8>] (handle_IPI+0x88/0x118)
[<c00138c8>] (handle_IPI+0x88/0x118) from [<c0008504>] (gic_handle_irq+0x58/0x60)
[<c0008504>] (gic_handle_irq+0x58/0x60) from [<c0012644>] (__irq_svc+0x44/0x78)
Exception stack(0xef099fa0 to 0xef099fe8)
9fa0: 00000001 ef092100 00000000 ef092100 ef098000 00000015 c0399f2c c0579d74
9fc0: 0000406a 413fc090 00000000 00000000 00000000 ef099fe8 c00666ec c000f46c
9fe0: 20000113 ffffffff
[<c0012644>] (__irq_svc+0x44/0x78) from [<c000f46c>] (arch_cpu_idle+0x34/0x3c)
[<c000f46c>] (arch_cpu_idle+0x34/0x3c) from [<c0053980>] (cpu_startup_entry+0xa8/0x10c)
[<c0053980>] (cpu_startup_entry+0xa8/0x10c) from [<000085a4>] (0x85a4)
We are in an interrupt context (IPI) and we are calling clk_get_rate in the
set_mode function which in turn ends up by getting a mutex... Even if that
does not hang, it is a potential kernel deadlock.
It is not allowed to call clk_get_rate() from interrupt context. To
avoid such calls the timer input frequency is stored in the driver's
data struct which makes it accessible to the driver in any context.
[dlezcano] completed the changelog with the WARN trace and added a more
detailed description. Tested on zync zc702.
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Tested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Bringing in the tegra dma/reset framework cleanup as a base for the DT changes.
* tegra/dma-reset-rework: (320 commits)
spi: tegra: checking for ERR_PTR instead of NULL
ASoC: tegra: update module reset list for Tegra124
clk: tegra: remove bogus PCIE_XCLK
clk: tegra: remove legacy reset APIs
ARM: tegra: remove legacy DMA entries from DT
ARM: tegra: remove legacy clock entries from DT
USB: EHCI: tegra: use reset framework
Input: tegra-kbc - use reset framework
serial: tegra: convert to standard DMA DT bindings
serial: tegra: use reset framework
spi: tegra: convert to standard DMA DT bindings
spi: tegra: use reset framework
staging: nvec: use reset framework
i2c: tegra: use reset framework
ASoC: tegra: convert to standard DMA DT bindings
ASoC: tegra: allocate AHUB FIFO during probe() not startup()
ASoC: tegra: call pm_runtime APIs around register accesses
ASoC: tegra: use reset framework
dma: tegra: register as an OF DMA controller
dma: tegra: use reset framework
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add support Octa Cores for exynos5420
: populate CPU node entries to 8 Cores
: extend mct to support 8 local interrupts
- Update dwmmc nodes for exynos5250 and exynos5420
: change status property of dwmmc nodes for exynos5250
: move dwmmc nodes from exynos5 to exynos5250 because
it's different between exynos5250 and exynos5420
: rename mmc nodes from dwmmc for exynos5 SoCs
: add dwmmc nodes for exynos5420
- Add G-Scaler nodes for exynos5420
- Add HS-i2c nodes in exynos5420
: High Speed I2C 7 channels (4 to 10)
- Update sysreg binding and node name in exynos4
- Update min voltage on exynos5250-arndale
- Move fifo-depth property from boards to exynos5250 SoC
: because the fifo-depth property is SoC specific
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Merge tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
From Kukjin Kim:
Samsung DT updates for v3.14
- Add support Octa Cores for exynos5420
: populate CPU node entries to 8 Cores
: extend mct to support 8 local interrupts
- Update dwmmc nodes for exynos5250 and exynos5420
: change status property of dwmmc nodes for exynos5250
: move dwmmc nodes from exynos5 to exynos5250 because
it's different between exynos5250 and exynos5420
: rename mmc nodes from dwmmc for exynos5 SoCs
: add dwmmc nodes for exynos5420
- Add G-Scaler nodes for exynos5420
- Add HS-i2c nodes in exynos5420
: High Speed I2C 7 channels (4 to 10)
- Update sysreg binding and node name in exynos4
- Update min voltage on exynos5250-arndale
- Move fifo-depth property from boards to exynos5250 SoC
: because the fifo-depth property is SoC specific
* tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Update Samsung sysreg binding document
ARM: dts: Fix sysreg node name in exynos4.dtsi
ARM: dts: Add hs-i2c nodes to exynos5420
ARM: dts: Update min voltage for vdd_arm on Arndale
ARM: dts: populate cpu node entries to 8 cpus for exynos5420
clocksource: mct: extend mct to support 8 local interrupts for Exynos5420
ARM: dts: Add device nodes for GScaler blocks for exynos5420
ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
ARM: dts: rename mmc dts node for exynos5 series
ARM: dts: Move fifo-depth property from exynos5250 board dts
ARM: dts: change status property of dwmmc nodes for exynos5250
ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
Since CSR SiRF was converted to multi platform in cf82e0e (ARM: sirf:
enable multiplatform support) the symbol CLOCK_TICK_RATE isn't the
platform specific definition any more, but a global dummy value. There
was no harm introduced in cf82e0e because the global value happens to
match the old platform specific one, still this dummy value isn't
intended to be used and will hopefully disappear soon, so introduce a
local #define and use that instead.
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Prepare the clock at probe time, as there is no other appropriate place
in the driver where we're allowed to sleep.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Exynos5420 is octa-core SoC from Samsung. Hence extend exynos-mct clocksource
driver to support 8 local interrupts.
Also extend dts entries for 8 interrupts.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Currently ARCH_BCM has been used for Broadcom
Mobile V7 based SoCs. In order to allow other Broadcom
SoCs to also use mach-bcm directory and files, this patch
renames the original ARCH_BCM to ARCH_BCM_MOBILE, and
uses ARCH_BCM to define any Broadcom chip residing
in mach-bcm directory.
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
bcm_timer_ids is no longer used after converting to CLOCKSOURCE_OF_DECLARE.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch removes the use of the IRQF_DISABLED flag.
It's a NOOP since 2.6.35 and it will be removed one day.
[dlezcano] : slightly changed the changelog
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch removes the use of the IRQF_DISABLED flag.
It's a NOOP since 2.6.35 and it will be removed one day.
[dlezcano] : slightly changed the changelog
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch removes the use of the IRQF_DISABLED flag
It's a NOOP since 2.6.35 and it will be removed one day.
[dlezcano] : slightly changed the changelog
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The driver core clears the driver data to NULL after device_release
or on probe failure. Thus, it is not needed to manually clear the
device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The driver core clears the driver data to NULL after device_release
or on probe failure. Thus, it is not needed to manually clear the
device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The current code sets the timer divider bits always. However, when
the 25 MHz timer is enabled, this is not needed and has no effect.
As this causes some confusion, rework the code so the divider is
set only when needed, i.e. when the 25 MHz timer is not in use.
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Many platforms rely on clocksource_of_init() being implicitly
called for registering clock sources and will get zero warnings
if no working clock source is available. Let's print a critical
error message if no clock source is found.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface. While we're here, mark the sched_clock function as
notrace to prevent ftrace recursion crashes.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.
Cc: Soren Brinkmann <soren.brinkmann@xilinx.com>
Cc: Michal Simek <monstr@monstr.eu>
Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface. While we're here increase the number of bits that
sched_clock can handle to 64 to make full use of the counter.
Cc: Stuart Menefy <stuart.menefy@st.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.
The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.
[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
alphabetically"
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
We want to keep this driver as the default provider of the clock events
and source, yet some other driver might fit in the "desired" category of
ratings. Hence, we need to increase a bit the rating so that we can have
more flexibility in the ratings we choose.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The interrupt for the timer is a shared processor interrupt, so any CPU
found in the system can handle it. Switch to our cpumask to
cpu_possible_mask instead of cpumask_of(0).
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
The clock event structure irq field was not filled previously to the
interrupt we're using.
This was resulting in the timer not being used at all when using a
configuration with SMP enabled on a system with several CPUs, and with
the cpumask set to the cpu_possible_mask.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
In commit 620f5e1cbf (dts: Rename DW APB timer compatible strings), both
"snps,dw-apb-timer-sp" and "snps,dw-apb-timer-osc" were deprecated in place
of "snps,dw-apb-timer". But the driver also needs to be udpated in order to
support this new binding "snps,dw-apb-timer".
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The read_sched_clock should return the ~value because the clock is a
countdown implementation. read_sched_clock() should be the same as
__apbt_read_clocksource().
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The sun4i timer can still be ticking when we enable the interrupt.
If another timer is actually used (A7 architected timer, for example),
odds are that the interrupt will eventually fire with the event_handler
pointer being NULL.
The obvious fix it to stop the timer before registering the interrupt.
Observed and tested on sun7i (cubietruck).
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
When booting a recent kernel on ARM with OF_DYNAMIC enabled, the kernel
warns about the following:
[ 0.000000] ERROR: Bad of_node_put() on /timer@50004600
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.12.0-rc5-next-20131017-00077-gedfd827-dirty #406
[ 0.000000] [<c0015b68>] (unwind_backtrace+0x0/0xf4) from [<c00117e4>] (show_stack+0x10/0x14)
[ 0.000000] [<c00117e4>] (show_stack+0x10/0x14) from [<c055f734>] (dump_stack+0x9c/0xc8)
[ 0.000000] [<c055f734>] (dump_stack+0x9c/0xc8) from [<c03b47d4>] (of_node_release+0x90/0x9c)
[ 0.000000] [<c03b47d4>] (of_node_release+0x90/0x9c) from [<c03b5084>] (of_find_matching_node_and_match+0x78/0xb4)
[ 0.000000] [<c03b5084>] (of_find_matching_node_and_match+0x78/0xb4) from [<c07887c8>] (clocksource_of_init+0x60/0x70)
[ 0.000000] [<c07887c8>] (clocksource_of_init+0x60/0x70) from [<c076e99c>] (start_kernel+0x1f4/0x33c)
[ 0.000000] [<c076e99c>] (start_kernel+0x1f4/0x33c) from [<80008074>] (0x80008074)
This is caused by clocksource_of_init() dropping a reference on the
device node that it never took. The reference taken by the loop is
implicitly dropped on subsequent iterations. See the implementation of
and the comment on top of the of_find_matching_node_and_match()
function for reference (no pun intended).
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
The time-efm32 driver uses the clocksource MMIO functions.
Thus it needs to select CLKSRC_MMIO in Kconfig.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Both platforms using the MTU (Nomadik and Ux500) have now been
converted to use device tree exclusively, thus let us delete
this platform data header and make this driver a fully
self-contained DT-only driver.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Lee Jones <lee.jones@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pavel Machek reports that this config is exposed on x86 where the
ARM architected timers aren't even present. Make it depend on the
ARM architected timers being selected so that non-ARM builds
aren't asked about it.
Reported-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Prepare the clock at probe time, as there is no other appropriate place
in the driver where we're allowed to sleep.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Fix the probe error path to release the clock resource when the
sh_tmu_register() call fails.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Prepare the clock at probe time, as there is no other appropriate place
in the driver where we're allowed to sleep.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Fix the probe error path to release the clock resource when the
sh_mtu2_register() call fails.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
IRQF_DISABLED is a no-op nowadays, so we can safely remove it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
We need to wait for at least 2 clock cycles whenever we reprogram our
clockevent timer. Report that the minimum number of ticks we can handle
is 3 ticks, and remove 3 ticks to the interval programmed to reflect
this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The Allwinner SoCs timer use the clocksource MMIO functions. We thus
need to select them in Kconfig.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
An efm32 features 4 16-bit timers with a 10-bit prescaler. This driver
provides clocksource and clock event device using one timer instance
each.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Add calls to clk_prepare and unprepare so that EMMA Mobile EV2 can
migrate to the common clock framework.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Commit:
65cd4f6 ("arch_timer: Move to generic sched_clock framework")
added code to register the arch_sys_counter in arch_timer_register(),
but it is already registered in arch_counter_register().
This results in the timer being added to the clocksource list twice,
therefore causing an infinite loop in the list.
Remove the duplicate registration and register the scheduler
clock after the original registration instead.
This fixes a hang during boot on Tegra114 (Cortex-A15).
[ While I've only tested this on Tegra114, I suspect the same hang
during boot happens for all processors that use this clock source. ]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: John Stultz <john.stultz@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/1381843911-31962-1-git-send-email-treding@nvidia.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Pull more timekeeping items for v3.13 from John Stultz:
* Small cleanup in the clocksource code.
* Fix for rtc-pl031 to let it work with alarmtimers.
* Move arm64 to using the generic sched_clock framework & resulting
cleanup in the generic sched_clock code.
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Register with the generic sched_clock framework now that it
supports 64 bits. This fixes two problems with the current
sched_clock support for machines using the architected timers.
First off, we don't subtract the start value from subsequent
sched_clock calls so we can potentially start off with
sched_clock returning gigantic numbers. Second, there is no
support for suspend/resume handling so problems such as discussed
in 6a4dae5 (ARM: 7565/1: sched: stop sched_clock() during
suspend, 2012-10-23) can happen without this patch. Finally, it
allows us to move the sched_clock setup into drivers clocksource
out of the arch ports.
Cc: Christopher Covington <cov@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Remove the deprecated IRQF_DISABLED flag.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Check function return values to avoid false positive driver init.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Adds support to configure the rate and enable the event stream for architected
timer. The event streams can be used to impose a timeout on a wfe, to safeguard
against any programming error in case an expected event is not generated or
even to implement wfe-based timeouts for userspace locking implementations.
This feature can be disabled(enabled by default).
Since the timer control register is reset to zero on warm boot, CPU PM notifier
is added to save and restore the value.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Pull (mostly) ARM clocksource driver updates from Daniel Lezcano:
" - Soren Brinkmann added FEAT_PERCPU to a clock device when it is local
per cpu. This feature prevents the clock framework to choose a per cpu
timer as a broadcast timer. This problem arised when the ARM global
timer is used when switching to the broadcast timer which is the case
now on Xillinx with its cpuidle driver.
- Stephen Boyd extended the generic sched_clock code to support 64bit
counters and removes the setup_sched_clock deprecation, as that causes
lots of warnings since there's still users in the arch/arm tree. He
added also the CLOCK_SOURCE_SUSPEND_NONSTOP flag on the architected
timer as they continue counting during suspend.
- Uwe Kleine-König added some missing __init sections and consolidated the
code by moving the of_node_put call from the drivers to the function
clocksource_of_init. "
Signed-off-by: Ingo Molnar <mingo@kernel.org>
The ARM architected timers keep counting during suspend so we can
mark this clocksource with the CLOCK_SOURCE_SUSPEND_NONSTOP flag.
This flag will indicate that this clocksource can be used for
calculating suspend time and injecting sleep time into the
timekeeping core. This should be more accurate than using an
external RTC or architecture specific persistent clock.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
These are all only called by dw_apb_timer_init which is an __init
function, too
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Instead of letting each driver call of_node_put do it centrally in the
loop that also calls the CLOCKSOURCE_OF_DECLARE callbacks. This is less
prone to error and also moves getting and putting the references into the
same function.
Consequently all respective of_node_put calls in drivers are removed.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: David Brown <davidb@codeaurora.org>
The arm_global_timer is a per cpu device. Set the appropriate flag.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Update to tip/timers/core and resolve minor conflict.
Conflicts:
drivers/clocksource/samsung_pwm_timer.c
Signed-off-by: John Stultz <john.stultz@linaro.org>
Few control settings done in architected timer as part of initialisation
can be lost when CPU enters deeper power states. They need to be
restored when the CPU is (warm)reset again.
This patch adds CPU PM notifiers to save the counter control register
when entering low power modes and restore it when CPU exits low power.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
The ARM architected timer can generate events (used for waking up
CPUs executing the wfe instruction) at a frequency represented as a
power-of-2 divisor of the clock rate.
An event stream might be used:
- To implement wfe-based timeouts for userspace locking implementations.
- To impose a timeout on a wfe for safeguarding against any programming
error in case an expected event is not generated.
This patch computes the event stream frequency aiming for a period
of 100us between events. It uses ARM/ARM64 specific backends to configure
and enable the event stream.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Will Deacon <will.deacon@arm.com>
[sudeep: moving ARM/ARM64 changes into separate patches
and adding Kconfig option]
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Update the STI driver by setting cpu_possible_mask to make EMEV2
SMP work as expected together with the ARM broadcast timer.
This breakage was introduced by:
f7db706 ARM: 7674/1: smp: Avoid dummy clockevent being preferred over real hardware clock-event
Without this fix SMP operation is broken on EMEV2 since no
broadcast timer interrupts trigger on the secondary CPU cores.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Clocksource devices provided by DT can be disabled (status != "okay").
Instead of registering clocksource drivers for disabled nodes, respect
the device's status by skiping disabled nodes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Some variants of Exynos MCT, namely exynos4210-mct at the moment, use
normal, shared interrupts for local timers. This means that each
interrupt must have correct affinity set to fire only on CPU
corresponding to given local timer.
However after recent conversion of clocksource drivers to not use the
local timer API for local timer initialization any more, the point of
time when local timers get initialized changed and irq_set_affinity()
fails because the CPU is not marked as online yet.
This patch fixes this by moving the call to irq_set_affinity() to
CPU_ONLINE notification, so the affinity is being set when the CPU goes
online.
This fixes a regression introduced by commit
ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API
which rendered all Exynos4210 based boards unbootable due to
failing irq_set_affinity() making local timers inoperatible.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Doug Anderson