also update the clk definitions in pxa27x and pxa3xx.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
MFP configurations after resume should be done before the GPIO registers
are restored. Move the mfp sysdev registeration to the same place where
GPIO and IRQ sysdev(s) are registered to better control the order.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
To further clean up the GPIO and IRQ structure:
1. pxa_init_irq_gpio() and pxa_init_gpio() combines into a single
function pxa_init_gpio()
2. assignment of set_wake merged into pxa_init_{irq,gpio}() as
an argument
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This makes the code better organized and simplified a bit. The change
will lose a bit of performance when performing IRQ ack/mask/unmask,but
that's not too much after checking the result binary.
This patch also removes the ugly #ifdef CONFIG_PXA27x .. #endif by
carefully not to access those pxa{27x,3xx} specific registers, this
is done by keeping an internal IRQ number variable. The pxa-regs.h
is also modified so registers for IRQ > PXA_IRQ(31) are made public
even if CONFIG_PXA{27x,3xx} isn't defined (for pxa25x's sake)
The incorrect assumption in the original code that internal irq starts
from 0 is also corrected by comparing with PXA_IRQ(0).
"struct sys_device" for the IRQ are reduced into one single device on
pxa{27x,3xx}.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The AC97 clock rate on PXA3xx is generated with a configurable divider
from sys_pll.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Expose control of the PXA3xx 13MHz CLK_POUT pin via the clock API
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is unnecessary since it is already protected by
spin_lock_irq{save, restore} in clock.c.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
According to PXA300/310 and PXA320 Developer manuals,
the ASCR[RDH] "bit needs to be cleared as part of the software
initialization coming out of any reset and coming out of D3".
The latter requirement is addressed by commit
"c4d1fb627ff3072", as for the former (coming out of any reset),
the kernel relies on boot loaders and assumes that RDH bit
is cleared there. Though, not all bootloaders follow the rule
so we have to clear the bit in kernel.
We clear the RDH bit in pxa3xx_init() function since
it is always invoked after any reset. We also preserve D1S, D2S
and D3S bits from being cleared in case we invoke pxa3xx_init()
function not from normal hardware reset (e.g. kexec scenario),
so these bits can be properly referenced later.
Signed-off-by: Dmitry Krivoschekov <dmitry.krivoschekov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1. clear RDH bit after resuming back from D3, otherwise, the multi function
pins will retain the low power state
2. save/restore essential system registers
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The original code incorrectly returns Hz instead of KHz.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Wakeup sources on PXA3 are enabled at two levels. First, the MFP
configuration has to be set to enable which edges a specific pin
will trigger a wakeup. The pin also has to be routed to a functional
unit. Lastly, the functional unit must be enabled as a wakeup source
in the appropriate AD*ER registers (AD2D0ER for standby resume.)
This doesn't fit well with the IRQ wake scheme - we currently do a
best effort conversion from IRQ numbers to functional unit wake enable
bits. For instance, there's several USB client related enable bits but
there's no corresponding IRQs to determine which you'd want. Conversely,
there's a single enable bit covering several functional units.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch is to add the third mmc controller support _only_
for pxa310.
On zylonite, the third controller support one slot.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch is to add the second mmc controller support for pxa3xx.
It's valid for pxa3[0|1|2]0.
On zylonite, the second controller has no slot.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patchis to add the first mmc controller support for pxa3xx.
It's valid for pxa3[0|1|2]0.
On zylonite, the first controller supports two slots, this patch
only support the first one right now.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Only register the MMC, framebuffer, I2C and FICP devices when the
platform supplies the necessary platform data structures for the
devices.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PXA3xx uses its own clk_pxa3xx_cken_ops, modify the code to use the
PXA3xx specific macros to define its clocks
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
eric miao