For a single image to support multiple SoCs(GART/SMMU).
Reported-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit adds device tree support for the GART hardware available on
NVIDIA Tegra 20 SoCs.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This must have been messed up while merging, the intention was
clearly to unlock there.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This
patch implements struct iommu_ops for GART for the upper IOMMU API.
This H/W module supports only single virtual address space(domain),
and manages a single level 1-to-1 mapping H/W translation page table.
[With small fixes by Joerg Roedel]
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Hiroshi Doyu