Commit Graph

5 Commits

Author SHA1 Message Date
Jayachandran B 0c8ba9d285 ASoC: Intel: Skylake: fix reset controller sequencing
MISCBDCGE is a new register for Misc Backbone clock gate control
which is useful to control while resetting the link and ensuring
controller is in required state so add API to control it

HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add
that while doing init chip and reset sequence.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-01-10 12:19:01 +00:00
Mousami Jana cce1c7f383 ASoC: Intel: Skylake: add LARGE_CONFIG_GET IPC support
For messages which have larger payload than mailbox data, we need
to split the payload using set of messages containing mailbox
size as payload.

For sending such payload we already support LARGE_CONFIG_SET
IPCs and now to query such payload add LARGE_CONFIG_GET IPC

Signed-off-by: Mousami Jana <mousami.janax@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-08 17:57:51 +00:00
Dharageswari R 6c5768b3aa ASoC: Intel: Skylake: Add support for Loadable modules
A module is loaded when the path consisting the module is opened.
The module binary(ies) is loaded from file system and cached in
kernel memory for future use. This is downloaded to DSP using DMA
and invoking Load module IPCs

This patch adds support for load/unload module IPCs, DMAing
modules and manging the modules

Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-08 17:57:51 +00:00
Jeeja KP 84c9e2836a ASoC: Intel: Skylake: Correct the runtime handler behaviour
On runtime pm resume, we need to download the firmware, also on
suspend we need to ensure all the interrupts from controller and
DSP are disabled.

Also since we download the firmware on resume, we don't need to do
so on init, so remove that bit

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-09 11:19:00 +01:00
Subhransu S. Prusty b81fd26359 ASoC: Intel: Add Skylake IPC library
This adds base SKL IPC library which uses common SST IPC lib.
Here we add definition for IPC types, sending and receiving IPC messages
from aDSP, handling interrupt, sending different types of messages etc

Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-07-09 18:33:23 +01:00