Commit Graph

722751 Commits

Author SHA1 Message Date
Yongqiang Sun 7a5086a71e drm/amd/display: Power down front end in init_hw.
front end is initialized during init_hw, but not
power gated. There are some left over valuse and will
cause some diags test failed. Power gated all front
end pipes will make sure every test has same starting
point.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:35 -05:00
Andrew Jiang 00893681a0 drm/amd/display: Reject PPLib clock values if they are invalid
We should be sticking with the default clock values if the values
obtained from PPLib are bogus.

Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:34 -05:00
Yue Hin Lau 62d591a8e0 drm/amd/display: create new files for hubbub functions
moving hubbub functions to new file

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:34 -05:00
Leo (Sunpeng) Li e1fc2dca12 drm/amd/display: Complete TODO item: use new DRM iterator
Abandon new_crtcs array and use for_each_new iterator to acquire new
crtcs.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:33 -05:00
Leo (Sunpeng) Li 8b8f27f972 drm/amd/display: Fix styling of freesync code in commit_tail
For better readability.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:33 -05:00
Christian König c1c7ce8f56 drm/amdgpu: move GART recovery into GTT manager v2
The GTT manager handles the GART address space anyway, so it is
completely pointless to keep the same information around twice.

v2: rebased

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:33 -05:00
Christian König 3da917b6c6 drm/amdgpu: nuke amdgpu_ttm_is_bound() v2
Rename amdgpu_gtt_mgr_is_allocated() to amdgpu_gtt_mgr_has_gart_addr() and use
that instead.

v2: rename the function as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:32 -05:00
Monk Liu 34a4d2bf06 drm/amdgpu:fix random missing of FLR NOTIFY
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:32 -05:00
Monk Liu 77a3c96b1b drm/amdgpu/sriov:fix memory leak in psp_load_fw
for SR-IOV when doing gpu reset this routine shouldn't do
resource allocating otherwise memory leak

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:31 -05:00
Monk Liu 503846e083 drm/amdgpu:cleanup ucode_init_bo
1,no sriov check since gpu recover is unified
2,need CPU_ACCESS_REQUIRED flag for VRAM if SRIOV
because otherwise after following PIN the first allocated
VRAM bo is wasted due to some TTM mgr reason.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:31 -05:00
Monk Liu 13a752e3a2 drm/amdgpu:cleanup in_sriov_reset and lock_reset
since now gpu reset is unified with gpu_recover
for both bare-metal and SR-IOV:

1)rename in_sriov_reset to in_gpu_reset
2)move lock_reset from adev->virt to adev

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:31 -05:00
Monk Liu 5740682e66 drm/amdgpu:implement new GPU recover(v3)
1,new imple names amdgpu_gpu_recover which gives more hint
on what it does compared with gpu_reset

2,gpu_recover unify bare-metal and SR-IOV, only the asic reset
part is implemented differently

3,gpu_recover will increase hang job karma and mark its entity/context
as guilty if exceeds limit

V2:

4,in scheduler main routine the job from guilty context  will be immedialy
fake signaled after it poped from queue and its fence be set with
"-ECANCELED" error

5,in scheduler recovery routine all jobs from the guilty entity would be
dropped

6,in run_job() routine the real IB submission would be skipped if @skip parameter
equales true or there was VRAM lost occured.

V3:

7,replace deprecated gpu reset, use new gpu recover

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:30 -05:00
Monk Liu 48f05f2955 amd/scheduler:imple job skip feature(v3)
jobs are skipped under two cases
1)when the entity behind this job marked guilty, the job
poped from this entity's queue will be dropped in sched_main loop.

2)in job_recovery(), skip the scheduling job if its karma detected
above limit, and also skipped as well for other jobs sharing the
same fence context. this approach is becuase job_recovery() cannot
access job->entity due to entity may already dead.

v2:
some logic fix

v3:
when entity detected guilty, don't drop the job in the poping
stage, instead set its fence error as -ECANCELED

in run_job(), skip the scheduling either:1) fence->error < 0
or 2) there was a VRAM LOST occurred on this job.
this way we can unify the job skipping logic.

with this feature we can introduce new gpu recover feature.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:30 -05:00
Christian König 3a393cf96a drm/amdgpu: fix indentation in amdgpu_display.h
That was somehow completely of.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:29 -05:00
Leo (Sunpeng) Li 1c77d4eea7 drm/amd/display: Only add stream to freesync when modeset required
This is a follow-up patch to:

Leo (Sunpeng) Li    Cleanup code that enables freesync

We should only add a stream to freesync if a modeset was requested, so
we don't fill the core freesync map with pointless streams.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:29 -05:00
Leo (Sunpeng) Li f01a2cf0a6 drm/amd/display: Cleanup code that enables freesync
This is a follow-up patch to:

Bhawanpreet Lakha    Atomic freesync ASSERT fix

Changes:
- Combine to use one iterator
- Use new DRM iterators.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:29 -05:00
Bhawanpreet Lakha bfe1708c80 drm/amd/display: Atomic freesync ASSERT fix
Changes to atomic set property for freesync.

Now In set property, just set the freesync variables and return 0.
Based on the variables call mod_freesync_set_user_enable() inside
commit_tail

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:28 -05:00
Alex Deucher 0858a8f204 drm/amd/display: add mod_freesync_user_enable to dm_connector_state
We don't currently expose variable refresh rate, but add the state to the
connector state to make it easier to maintain the support for it from a
hw support perspective while we figure out the uapi for drm.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:41:15 -05:00
Anthony Koo 4952d4c584 drm/amd/display: DMCU FW loading from PSP
Update the programming sequence to allow DMCU firmware to be loaded by
PSP. This code detects whether the firmware is loaded and does a check
to verify the expected interface version and checks for correct response
from micro controller.

Added registry key method to allow force loading of firmware from kernel
mode driver for test purposes. This is old method of firmware loading
without PSP.

Moved some init sequences into dc/dmcu.

Changed loading sequence to initialize IRAM after firmware completely
loaded. Firmware will now disable features that use IRAM
until initialized.

Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:23 -05:00
Yongqiang Sun 7d2638a61a drm/amd/display: Set cursor position as per address.
In case of pipe split, cursor position should also be
programmed as per cursor address.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:23 -05:00
Harry Wentland 59c185ac4e drm/amd/display: Explicit casting for grph object ids
C++ compilers don't like the implicit conversion

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:22 -05:00
Yue Hin Lau c42c275ce3 drm/amd/display: cleaning up hubp for dcn
removing duplicate functions, renaming struct mi_regs, etc.

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:22 -05:00
Harry Wentland e643b1d53d drm/amd/display: Clean some unneeded defines from ddc_service_types.h
Remove defines we no longer need

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:22 -05:00
Harry Wentland 8474a22b54 drm/amd/display: Cleanup some fail labels in dcn10_resource
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:21 -05:00
Mikita Lipski d182fddbc7 drm/amd/display: Adding DCN1 registers
Registers added to definition list that are required
for multi display synchronization

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:21 -05:00
Yongqiang Sun 4c7d45fae8 drm/amd/display: Check cursor address before program.
Program cursor attributes during set mode is only needed
in case of pipe slipt, bottom pipe should be programmed
same as top pipe. Need to program if address is 0.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:20 -05:00
Yongqiang Sun 3dc780ec34 drm/amd/display: Move lock to front end program.
Moved lock and unlock to apply_ctx_to_surface, since all
the front end programming is within apply_ctx_to_surface.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:20 -05:00
Anthony Koo 553aae12e3 drm/amd/display: Add APU cap in dc_caps
Some features should only be enabled on APUs or should not
be enabled on APUs.

Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:20 -05:00
Rex Zhu 433f1aa786 drm/amdgpu: delete duplicated code.
the variable ref_clock was assigned same
value twice in same function.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:19 -05:00
Rex Zhu 95a3ff787a drm/amd/pp: delete an outdated comment in amd_powerplay.c
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:19 -05:00
Rex Zhu 4c7c8bbb1f drm/amd/pp: implement notify_smu_memory_info on Powerplay
Used to set up smu power logging.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:19 -05:00
Rex Zhu d668942bb8 drm/amdgpu: add new pp function point notify_smu_memory_info
Used to set up smu power logging.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:18 -05:00
Rex Zhu c79563a316 drm/amdgpu: add header kgd_pp_interface.h
move powerplay and amdgpu shared structures
and definitions to kgd_pp_interface.h.  This
is the interface between the base driver
and powerplay.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:18 -05:00
Rex Zhu 11dc9364bd drm/amdgpu: move struct amd_powerplay to amdgpu.h
Clean up the interface.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:17 -05:00
Rex Zhu f685d71432 drm/amd/powerplay: move functions to amd_pm_funcs table
those functions are exported to DC

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:17 -05:00
Rex Zhu 2c2b67b479 drm/amdgpu: move DC and PP shared data structures to dm_pp_interface.h
Move the display/power interfaces to one place.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:17 -05:00
Christian König 4ff23be3d5 drm/amdgpu: remove extra parameter from amdgpu_ttm_bind() v2
We always use the BO mem now.

v2: minor rebase

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:16 -05:00
Christian König 2a018f28a8 drm/amdgpu: don't wait interruptible while binding GART space
Display can't seem to handle this correctly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:16 -05:00
Christian König f5318959b5 drm/amdgpu: fix pin domain compatibility check
We need to test if any domain fits, not all of them.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:16 -05:00
Christian König ead282a4f5 drm/amdgpu: always bind pinned BOs
We always need to bind pinned BOs, not just when the caller requested the
address.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:15 -05:00
Christian König 5e91fb57eb drm/amdgpu: use the actual placement for pin accounting
This allows us to specify multiple possible placements again.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:15 -05:00
pding 8840a3878d drm/amdgpu: retry init if it fails due to exclusive mode timeout (v3)
The exclusive mode has real-time limitation in reality, such like being
done in 300ms. It's easy observed if running many VF/VMs in single host
with heavy CPU workload.

If we find the init fails due to exclusive mode timeout, try it again.

v2:
 - rewrite the condition for readable value.

v3:
 - fix typo, add comments for sleep

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: pding <Pixel.Ding@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:14 -05:00
pding b59142384e drm/amdgpu/virt: implement wait_reset callbacks for vi/ai
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: pding <Pixel.Ding@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:14 -05:00
Evan Quan 7413d2faef drm/amd/powerplay: describe the PCIE link speed in right GT/s
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:14 -05:00
pding b636176efd drm/amdgpu/virt: add wait_reset virt ops
Driver can use this interface to check if there's a function level
reset done in hypervisor. It's helpful when IRQ handler for reset
is not ready, or special handling is required.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: pding <Pixel.Ding@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:13 -05:00
pding a16f8f11c5 drm/amdgpu/virt: add function to check MMIO (v2)
MMIO space can be blocked on virtualised device. Add this
function to check if MMIO is blocked or not.

Todo: need a reliable method such like communation
with hypervisor.

v2:
 - add comments inline

Signed-off-by: pding <Pixel.Ding@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:13 -05:00
pding 1366b2d016 drm/amdgpu: avoid soft lockup when waiting for RLC serdes (v2)
Normally all waiting get timeout if there's one.
Release the lock and return immediately when timeout happens.

v2:
 - set the se_sh to broadcase before return

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: pding <Pixel.Ding@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:13 -05:00
pding 9953b72f9c drm/amdgpu: change redundant init logs to debug level
When this VF stays in exclusive mode for long, other VFs will be
impacted.

The redundant messages causes exclusive mode timeout when they're
redirected. That is a normal use case for cloud service to redirect
guest log to virtual serial port.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: pding <Pixel.Ding@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:12 -05:00
Monk Liu bc1b1bf6e3 drm/amdgpu:implement ctx query2
this query will give flag bits to indicate what happend
on the given context

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:12 -05:00
Monk Liu 668ca1b44d drm/amdgpu:don't change ctx->reset_couner upon query
reset_counter marks the reset counter number once the context
is created, shouldn't be changed due to query.

To keep U/K interface on the ctx_query and keep ctx's reset_counter
logic compatible with GPU RESET feature, now use another var named
"reset_counter_query" to replace the original checked & updated in
amdgpu_ctx_query.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04 16:33:11 -05:00