STiH415/6 SoC support is being removed from the kernel.
This patch updates the ST pinctrl dt doc and removes
references to these obsolete platforms. It also updates
the dt example to the currently supported STiH407
platform.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Cc: <linus.walleij@linaro.org>
Cc: <robh+dt@kernel.org>
Cc: <linux-gpio@vger.kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch allows to use the second parameter of gpio
specifier, which is used to specify whether the gpio is
active high or low.
Simply remove specific of_xlate callback() and of_gpio_n_cells
and use default one set by of_gpiochip_add() which allows
to use second parameter gpio specifier.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
s/interrupts-names/interrupt-names/g
s/clocks-names/clock-names/g
Some of the binding files and device tree files get this wrong and the
kernel won't be able to pick it up. Fix them up now so that they don't
get widely used.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by : Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Grant Likely <grant.likely@linaro.org>
This patch add interrupt support to the pincontroller driver.
ST Pincontroller GPIO bank can have one of the two possible types of
interrupt-wirings.
First type is via irqmux, single interrupt is used by multiple gpio
banks. This reduces number of overall interrupts numbers required. All
these banks belong to a single pincontroller.
_________
| |----> [gpio-bank (n) ]
| |----> [gpio-bank (n + 1)]
[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
| |----> [gpio-bank (... )]
|_________|----> [gpio-bank (n + 7)]
Second type has a dedicated interrupt per gpio bank.
[irqN]----> [gpio-bank (n)]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through the PIO
multiplexing block. Each pin supports GPIO functionality (ALT0) and
multiple alternate functions(ALT1 - ALTx) that directly connect the pin
to different hardware blocks. When a pin is in GPIO mode, Output Enable
(OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
block. Otherwise the PIO multiplexing block configures these parameters
and retiming the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Peter Griffin