This patch adds support for the GPIO/pinmux controller found on the VIA
VT8500 and Wondermedia WM8xxx-series SoCs.
Each pin within the controller is capable of operating as a GPIO or as
an alternate function. The pins are numbered according to their control
bank/bit so that if new pins are added, the existing numbering is maintained.
All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and
WM8850.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This fix allows to correctly select default and
alternate pin mode.
By default for all ABx500 family chip, pin default
mode is selected by clearing corresponding bit in
GPIOSELx register except for pins which support
alternate function, in this case, corresponding bit
must be set.
But, due to an unlogical hardware implementation,
for one particular pin (GPIO11) reverse setting
must be done. For that, update the alternate function
array by declaring that this pin supports alternate
function.
Same issue has been fixed in pinctrl-ab8505.c
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I accidentally left this patch:
commit 6f9e41f4e6
"pinctrl/pinconfig: add debug interface"
in the tree though the patch was not yet finished.
Revert it partially (we need the infrastructural changes).
Cc: Laurent Meunier <laurent.meunier@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a simple device tree binding for db8540 boards.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@stericsson.com>
Reviewed-by: Philippe Langlais <philippe.langlais@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Instead of just enabling the settings that were disabled in the 1st
loop, it's simpler to recall pinctrl_select_state with the old state.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As Stephen Warren pointed out, pinctrl_free_setting() was called instead
of pinmux_disable_setting() on error.
In this error code, we want to call pinmux_disable_setting() where
pinmux_enable_setting() was called.
And when pinconf_apply_setting() was called, we can't do much to undo
the pin muxing (the closest thing I can think about for "unmuxing" a pin
is muxing it as GPIO input).
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pointer "port" is always not NULL if gpio->port_list is not empty.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In unapply_new_state, the old state is re-applied, but p->state is not
set back as it should.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As Stephen Warren suggested, checking first if the setting->node entry
is the first in the list or not is superfluous, as it is checked again
in the list_for_each_entry bellow.
So, remove it, the code will be simpler and lighter !
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For the port controller to work, we need to enable the apb0_pio gate.
This commit adds the ability to enable one clock specified on the device
tree to the pinctrl driver.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In file included from drivers/pinctrl/core.c:30:0:
include/asm-generic/gpio.h: In function 'gpio_get_value_cansleep':
include/asm-generic/gpio.h:270:2: error: implicit declaration of
function '__gpio_get_value' [-Werror=implicit-function-declaration]
include/asm-generic/gpio.h: In function 'gpio_set_value_cansleep':
include/asm-generic/gpio.h:276:2: error: implicit declaration of
function '__gpio_set_value' [-Werror=implicit-function-declaration]
drivers/pinctrl/core.c: In function 'pinctrl_ready_for_gpio_range':
drivers/pinctrl/core.c:297:9: error: implicit declaration of function
'gpio_to_chip' [-Werror=implicit-function-declaration]
drivers/pinctrl/core.c:297:27: warning: initialization makes pointer
from integer without a cast [enabled by default]
drivers/pinctrl/core.c:304:45: error: dereferencing pointer to
incomplete type
drivers/pinctrl/core.c:305:26: error: dereferencing pointer to
incomplete type
drivers/pinctrl/core.c:305:39: error: dereferencing pointer to
incomplete type
cc1: some warnings being treated as errors
make[2]: *** [drivers/pinctrl/core.o] Error 1
make[1]: *** [drivers/pinctrl] Error 2
make[1]: *** Waiting for unfinished jobs....
It's caused by CONFIG_GPIOLIB isn't enabled for some platform. So
add the dependence on pinctrl_ready_for_gpio_range().
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This fix allows to correctly select default and
alternate pin mode.
By default for all ABx500 family chip, pin default
mode is selected by clearing corresponding bit in
GPIOSELx register except for pins which support
alternate function, in this case, corresponding bit
must be set.
But, due to an unlogical hardware implementation,
for one particular pin (GPIO11) reverse setting
must be done. For that, update the alternate function
array by declaring that this pin supports alternate
function.
Reported-by: Ramesh Chandrasekaran <ramesh.chandrasekaran@stericsson.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Highlights:
* Add Lager board support
* Add ape6evm board support
* Add Bock-W board support
* Mackerel MMCIF/SDHI clean ups
* Add ethernet support to kzm9g-reference
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10
The merge with renesas-pinmux2-for-v3.10 was made to provide
run-time dependencies for the following changes:
ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRW4ucAAoJENfPZGlqN0++oHQP/jpJ6AAAwuFfcfPSnpWIkJY6
cidxxBwf445EcW1OXAKez4Ki4gJ8+AcYBp39dm5nm1HUSrmJgOVgbeQ/benakUi/
5/Qgj0Hi4HmiYzrDuZo1SgBu3iHZy38KzbzpUFwBXYJW3snlM4WYET08FHzun/3j
hvWI5fEgYC4FBzbU68Vc6R1aCZM+yio1wezRz+zMjkSJ2f6dGwM16oXbh0nLgWKk
VdvAOTmNbzFIs/3frATcozBI956SJPha7SMq7YUSE0MRIcjpTtvhGnnWFyq3NQH6
JeSs7qKcXBJ8foOE333J+KGyXpMp/FgJxQo0C3N3/fbaiPH6+eE0gkRL27MUPdRy
EES9FPGSzuDEe6WPG9pUOJEbkD3BjBUuokC8LDCPrFK1jXdPtz2yAeNOAz+sLDLe
oYpmlE2D8dG7DbxrFNRrhFGgujHI4gV9I54IM58xEq3+MpzK0GS4GYYf3+Qas7ob
P5qDenAIEC5b+Ox578iRyy35kP8cwbm9BV7zLAXCLVTjWEjcAWPRi+6r9TYt7DV1
/FzW2csVqyN/ec6WljJblImty1tvV1GuuHPQ8azu6ZHlxXQDPAo5KIROTVW/ud7m
daReu65vkGwN8PMPpT/jMh38b8wGBkR9TgI2vCLOQ95PTY1UVdkyZIynUkMV5jX8
PxkEzDA3qHoMDI4/XPbD
=Zhif
-----END PGP SIGNATURE-----
Merge tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2
Third round of Renesas ARM SoC board updates for v3.10
Highlights:
* Add Lager board support
* Add ape6evm board support
* Add Bock-W board support
* Mackerel MMCIF/SDHI clean ups
* Add ethernet support to kzm9g-reference
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10
The merge with renesas-pinmux2-for-v3.10 was made to provide
run-time dependencies for the following changes:
ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support
* tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (307 commits)
ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection
ARM: shmobile: mackerel: add interrupt names for SDHI0
ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio
ARM: shmobile: mackerel: remove OCR masks, where regulators are used
ARM: shmobile: mackerel: SDHI resources do not have to be numbered
ARM: shmobile: Initial r8a7790 Lager board support
ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support
ARM: shmobile: APE6EVM base support
ARM: shmobile: kzm9g-reference: add ethernet support
ARM: shmobile: add R-Car M1A Bock-W platform support
sh-pfc: r8a73a4: Remove unused GPIO bias data
ARM: shmobile: r8a73a4: Remove all GPIO enums
sh-pfc: r8a73a4: Remove function GPIOs
ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
sh-pfc: r8a73a4: Remove IRQC function GPIOS
sh-pfc: r8a73a4: Remove SCIF function GPIOS
sh-pfc: r8a73a4: Add IRQC pin groups and functions
sh-pfc: r8a73a4: Add SCIF pin groups and functions
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Highlights:
* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRW4oIAAoJENfPZGlqN0++W6MP/2+++lzClm3iPneAhigO5UAB
IF0/CSLYAHjxlMW4CZWquJE6t9x5MptcAi2GmBwPwRFsQWjz6jFIHSmtEavX81IU
0k0zBf2QEHED+PhEx50V3TvDyLAf6pAWWWN/Fp5r8isLrUXAoZhY2eY6vaddFQkY
a98NC7c8t911stOs0BDeiQ9TjsR8P1uRYIPang473NOOQ8w6vf5CPh7ihcG4026A
R5AomkOZgNukF55gxi1BfUfaXpVsuBhRb5PfdzPXbNB3fOybaPSEc+rnFoCwe5DY
teQbpldHFp0wHMFYOZ+mlGqToDitLyqk1D98U7KNNAKnzX74VW4ta15pkK+Pmed+
m4a/eeJIv4y1Xfk06wwj78SvT7uW+u24iUW0mppuH/x5gGjPD9q56rA4ylguV0XF
AeVeBiA/cMlDK2k5lw087fyORvvVX4tDY5P7X7BxLCVuZRFynoNJLkXyvE/0yI3R
UvrxlajIEUVXtK1uMh4ULLbP4OiA2SMhqrLqG+JvibeFFWLY0mxj+IDRuv34/UqR
iQUMkCIjOJ2Xxcs5rWr9fRHiuUL66Xy8+FE1jL/Wkb6qldmbtcBbn9le2CUucPQ7
McXa3R8x46qMaG40b5wCxAv7W6zOcpHNl0YnwNh7ClD+BctjF2JpVLmJQZsQqyyn
FKPpzmdXD3eIL1g3R58L
=vwDo
-----END PGP SIGNATURE-----
Merge tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10
Highlights:
* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
* tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (185 commits)
sh-pfc: r8a73a4: Remove unused GPIO bias data
ARM: shmobile: r8a73a4: Remove all GPIO enums
sh-pfc: r8a73a4: Remove function GPIOs
ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
sh-pfc: r8a73a4: Remove IRQC function GPIOS
sh-pfc: r8a73a4: Remove SCIF function GPIOS
sh-pfc: r8a73a4: Add IRQC pin groups and functions
sh-pfc: r8a73a4: Add SCIF pin groups and functions
sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support
sh-pfc: r8a73a4: GPIO IRQ support
sh-pfc: r8a73a4: Support sparse GPIO numbers
sh-pfc: Add r8a73a4 pinmux support
sh-pfc: r8a7779: Split DU input and output pixel clocks
sh-pfc: r8a7779: Remove GPIO data
ARM: shmobile: r8a7779: Register GPIO devices
sh-pfc: Configure pins as GPIOs at request time when handled externally
sh-pfc: Skip gpiochip registration when no GPIO resource is found
sh-pfc: Make GPIO support optional
sh-pfc: Make function GPIOs support optional
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Some Highlights:
* Add r8a7790 SoC
* Add r8a73a4 SoC
* Migrate r8a7740 SoC from INTC to GIC
* Add thermal driver support to r8a73a4 SoC
* Add irqpin DT nodes to sh73a0 SoC
* Add SCIF support to r8a7778 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-intc-external-irq2-for-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRWmXUAAoJENfPZGlqN0++r7YQAI47GqgjuqQsE4XUGaM12Rxz
vTpJ4l9AfDcZxnLbRG80QuMYUInhiBExH1MA3wtAmgLRNpFOOUH12rM54Y8M5oLy
AbN/rvf7ReM0eQBlBlu7TUAUxPLRMzTyo1auBXIFM3Qjp5udf5bd3eFWBduQhaIA
ltr+7czw96KpHtprbeRjR5qelFXATF9kW0rI8E9CRb6lLrHQ6BS7HO6UH5AcnB5V
8iVj/hWFV11KKsiP+BJDa8pXqFJUjAeYipYJ7wA0cTqKz3IgHnHnEcsyGmSmjHoX
NOxPZWB9b5zYNn5dXdyTlpHC592hdS4EPGuzlHceiphxFvJ5Ay83b3braU5SUd0O
ArzDg/acR2Uov35wWYPoiAkQMaf1U97TEUw4q5+bO4r+12SIt+iuevQkYx72YZjR
qVcCK895y0sMyfRafcz9Apoy8Rnimjfc+dMOebt2lHE33tXCZ4KxD+YVTeNm5OIG
/QqVZuqi4DzSpQgJwpYf9DlRCNg2PKA8r+0pBT+xRDDj+MPbw10IMHjx/ZNJthvX
r9yyupNEsa1goT7wbDHq5bJw41D5JGldYlKZz6Tz0h7eQFPdSkE6F1Usa74fMKSF
VcAlvKmb7rR/ZRWILKGrPKTAzZKedSY6RYmhJEgSxnYQYt2fmUu6bAIu09s9J6BC
XEC7K7rRuQh1C6vu/t/D
=jivx
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
Second round of Renesas ARM SoC updates for v3.10
Some Highlights:
* Add r8a7790 SoC
* Add r8a73a4 SoC
* Migrate r8a7740 SoC from INTC to GIC
* Add thermal driver support to r8a73a4 SoC
* Add irqpin DT nodes to sh73a0 SoC
* Add SCIF support to r8a7778 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-intc-external-irq2-for-v3.10
* tag 'renesas-soc2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (88 commits)
ARM: shmobile: r8a7790 SoC 64-bit DT support
ARM: shmobile: r8a73a4 SoC 64-bit DT support
ARM: shmobile: r8a7790 PFC support
ARM: shmobile: r8a7790 IRQC support
ARM: shmobile: r8a7790 SCIF support
ARM: shmobile: Initial r8a7790 SoC support
ARM: shmobile: r8a7779: move global functions to r8a7779.h
ARM: shmobile: r8a7740: move global functions to r8a7740.h
ARM: shmobile: sh73a0: move global functions to sh73a0.h
ARM: shmobile: sh7372: move global functions to sh7372.h
ARM: shmobile: r8a7779: remove DIV4 clocks and use fixed ratio clock
ARM: shmobile: r8a7740: use fixed ratio clock
ARM: shmobile: r8a7740: tidyup comment/implementation mismatch
ARM: shmobile: sh73a0: use fixed ratio clock
ARM: shmobile: sh7372: use fixed ratio clock
ARM: shmobile: add struct clk_ratio and fixed ratio clock macro
ARM: shmobile: sh7372: remove DIV4_ZT* clocks
ARM: shmobile: sh73a0: remove DIV4_ZT* clocks
ARM: shmobile: sh73a0: add a TWD clock
ARM: shmobile: r8a7740: Migrate from INTC to GIC
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Remove unused pull-up/down data from the r8a73a4 PFC code.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a73a4 platforms use the pinctrl API to control pin functions.
Function GPIOs are no longer needed.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a73a4 board support will use the pinctrl API to control the
external IRQ pins so remove the unused function GPIOS.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a73a4 board support will use the pinctrl API to control the SCIF
pins, remove the corresponding unused function GPIOS.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
V2 of PINCTRL support for r8a73a4 IRQC hardware
and in particular the external pins IRQ0 -> IRQ57.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Implement pull-up/down support for r8a73a4 similar to the implementation
for sh73a0.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
V2 of code to add GPIO -> IRQ mappings to the
PFC table for the r8a73a4 SoC. Requires the IRQs
to be mapped at a fixed location in Linux IRQ
space. The actual IRQs are not handled by the
PFC, instead IRQC is used on r8a73a4.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers
in the PFC SoC data. Pin numbers shall be used with the GPIO API from
this point on.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial PFC support for the r8a73a4 SoC.
At this point only GPIO interface is supported, move to newer interfaces
planned as incremental changes.
Original authors are Morimoto-san with help from Yoshii-san, thanks to
them for the heavy lifting. Adjusted by Magnus to work together with
updated code in drivers/pinctrl.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Takashi Yoshii <takashi.yoshii.zj@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The output pixel clocks can be used without the input pixel clocks.
Split them in different groups.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
GPIOs are now handled by a separate driver, remove GPIO data from the
SoC information structure.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When a GPIO is handled by a separate driver the pinmux
gpio_set_direction() handler won't be called. The pin mux type then need
to be configured to GPIO at request time.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Boards/platforms that register dedicated GPIO devices will not supply a
memory resource for GPIOs. Try to locate the GPIO memory resource at
initialization time, and skip registration of the gpiochip if the
resource can't be found.
This is a temporary modification to ease the transition to separate GPIO
drivers. It should be reverted when all boards and platforms will have
been moved.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When implemented as a separate IP block, GPIOs should be handled by a
separate driver. To make this possible GPIO support needs to be optional
in the sh-pfc driver.
If no GPIO data registers are supplied in the SoC information structure
skip registration of the gpiochip.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The target is to get rid of function GPIOs completely. To reach this,
make function GPIOs support optional by skipping the function GPIO chip
registration if no function GPIOS are defined in SoC data.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Refactor the GPIO macro magic to use GPIO numbers directly instead of
the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum
entries from the mach/r8a7779.h header.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7779 platforms use the pinctrl API to control functions. Function
GPIOs are unused and unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The sh_pfc_phys_to_virt() function ends with a BUG() statement without a
return. When CONFIG_BUG isn't set the function will thus have no return
value. Fix it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Conflicts:
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
This merge is to provide r8a73a4 SoC files, which are added in the
soc branch and depended on by r8a73a4 pfc-changes which are to
be added to the pinmux branch.
With the added capabilty of the intc_irqpin driver to handle shared
external IRQs, all prerequisites are fulfilled and we are ready to
migrate completely to GIC. This includes the following steps:
- Kconfig: select ARM_GIC and RENESAS_INTC_IRQPIN
- intc-r8a7740: Throw out all legacy INTC code and init the GIC. We need
to mask out all shared IRQs as it is needed by the
shared intc_irqpin driver.
- setup-r8a7740: Add 4 irqpin devices to handle external IRQs and update
all IRQ numbers to point to the GIC SPI.
- board-armadillo: Update all IRQ numbers to point to the GIC SPI.
- pfc-r8a7740: Update all IRQ numbers of the GPIOs to point to the GIC
SPI.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
While investigating (ab)use of krealloc, David found this bug. It's
unlikely to occur, but now we detect the condition and error out
appropriately.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If a new state is applied, the groups configured in the old state but
not in the new state are disabled.
If something goes wrong and the new state can't be applied, we have to
re-enable those groups.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If enabling a pin fails in pinctrl_select_state_locked(), all the
previous enabled pins have to be disabled to get back to the previous
state.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This prepares the implementation of pinctrl_select_state_locked() free code.
No functionnal change.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Clearly, "node" was meant instead of "not"
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Using for_each_set_bit() to simplify the code.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following checkpatch error:
ERROR: space required before the open parenthesis '('
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following type of checkpatch errors:
ERROR: space required before the open parenthesis '('
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'conf_items' is used only in this file. Silences the below
sparse warning:
drivers/pinctrl/pinconf-generic.c:37:24: warning:
symbol 'conf_items' was not declared. Should it be static?
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following types of checkpatch errors:
ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: space required before the open parenthesis '('
ERROR: "(foo*)" should be "(foo *)"
ERROR: space required after that ',' (ctx:WxV)
ERROR: "(foo*const*)" should be "(foo *const*)"
ERROR: space required before that '*' (ctx:VxB)
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
sizeof() when applied to a pointer typed expression gives the
size of the pointer, not that of the pointed data.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following types of checkpatch errors:
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that close parenthesis ')'
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Silences the following type of checkpatch errors:
ERROR: space required after that ',' (ctx:VxV)
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl-pxa driver doesn't support well on DT mode. Now pinctrl-single
could support DT mode & pin configuration. Use pinctrl-single driver to
support MMP/PXA silicons instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These functions have been introduced by commit 10a8c383 (irq: introduce
entry and exit functions for chained handlers) in asm/mach/irq.h. This
patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
drivers do not rely on architecture specific header files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
The sirf platforms use no hardcoded IRQ numbers, so there is no reason to
use the legacy domain, and by converting to the linear domain, we get
a more efficient representation of sparse IRQs and remove the dependency
on the mach/irqs.h header file.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
- Usecount bounds checking so we do not go below zero on
mux usecounts.
- Loop range checking in GPIO ranges in the DT range parser.
- Proper print in debugfs for pinconf state.
- Fix compilation bug in generic pinconf code.
- Minor bugfixes to abx500 and mvebu drivers.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJRS1t1AAoJEEEQszewGV1zV9EP/jb34Bk5gjeDFg5+tFYTRTyn
RUq69aN20hTrmFkTYqF5oP6e+4QU6WMuLOkuQCcLIzxaA8IgCr75qKzetzF7kWjx
ymR8t0wtI34r8mw4D+SNEg3Jz/99IIDmZP3lMd7A6Pccz0TsGQ4J78m5l2MPPnXt
pQRtixyoLocJOwum5UTVaKj5s8zPwZR3LyRk9bXRk6hbVRvmYEv/N6xTIZE5SjwF
QaBrBHUd4ZTvQIqYk1ECOoUpvZecE8FDIewybcZfIzHr0KCZdLAXYuW94k4GY/J3
bI7OwHX576N4GrNWnYHklapN4SY+DFdMXHREaFbAi+Ei3gPyA3DJ1mtr33Fj5Mgk
hucvU3a4ZvgEKIOPorW0ZINllwWkQGkmeZ7uqSRS17RYRyjc6tW51PMGhcx55cmB
RCosGhwWeKU8zX9Hs8QiVprigtjpFNx8o8baEOqtKYgXa+jnsgPghJkGLbfhDYCV
c9mmrKzU6fD9Si9X8Yf9WoN+z1hy/UpL4NhetaFt1kUAcDXEHGwMhSz8Wt+FTXYw
XjpJ3FHzyFlxiQStzORy15E6O7PFEmfDuFca1P8Zj9MKcqvgFg0aLpaqJir7/U+e
fjYwpMVQzv6f1ZmxbOtYbzBMVJst7g6RFJh6AjxfuI5p//j44VfOTinBNrDAQ5a9
X/1cEY6m5Q+x9gKmtYvd
=9iL3
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-fixes-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl fixes from Linus Walleij:
"Here are a few pinctrl fixes for the v3.9 rc series:
- Usecount bounds checking so we do not go below zero on mux
usecounts.
- Loop range checking in GPIO ranges in the DT range parser.
- Proper print in debugfs for pinconf state.
- Fix compilation bug in generic pinconf code.
- Minor bugfixes to abx500 and mvebu drivers."
* tag 'pinctrl-fixes-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinmux: forbid mux_usecount to be set at UINT_MAX
pinctrl: mvebu: fix checking for SoC specific controls
pinctrl: generic: Fix compilation error
pinctrl: Print the correct information in debugfs pinconf-state file
pinctrl: abx500: Fix checking if pin use AlternateFunction register
gpio: fix wrong checking condition for gpio range
If pin_free is called on a pin already freed, mux_usecount is set to
UINT_MAX which is really a bad idea.
This will issue a warning, so that we can correct the code responsible
for the double free.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch fixes a minor bug (probably due to a typo) while checking
the SoC specific controls in mvebu_pinctrl_probe().
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This provides two new INTC drivers for use with Renesas ARM-based SoCs and
makes use of them on the r8a7779 and sh73a0 SoCs.
It has been agreed by the relevant parties, Thomas Gleixner, Magnus Damm,
and myself that it would be best to merge this code through the renesas
tree and thus through the arm-soc tree.
This is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRR8KvAAoJENfPZGlqN0++MdQP/jxDtb26s5ud1Th3GOMrvWcb
xFhZnnAp7wawPmbXT/l0lvMQSjTgPunTgUCD2RSp4CUKquG+sMNvmt+oxZT/WG81
VLbjicQWIdcODt/gkuff4U282s3Kk7joRdzfORUKSu3/tjfy1nBSyGdJBVaGmor4
NL0rbtuhnf3Jng4+u/UgtcsA6FVmnACf9T2m8Gpf9JbcnJXd/U7jurk9ZY8VvEti
KsbmlfmfBXLVjyl0Glbik07Njs4Jta9NIZ6hj9Yrlb8p0/EqjbRvuqDn3nLLIKpd
LhdkOLm7V7X2r7T4aDc1yvZxlqWTy15U/HJTnKxcW+Phl+p6mY7Kmiwab9ImQ5ZP
hG+GjEcznHs9kDgxceKcj8CCKFrP3zH8w0k+PIb76jEG7ttWHbF/3mr35gWIXKYe
duKrHoA9Y+qssB/rOZw0i4GNb2QXpyTHDpoFMXc9jDpRzJHBXwsrJDJTJQ6NQlfJ
HhlCdLv3fUeyJpYBlzrFkqoyt1wHx++pkQnO0yEzGTetNXrNuUBuDqiJnbwfBznp
wMNkQh4s3zc/Cn4HziLc78cWmoov42xSAuEcbnsD9Cg3wtfdtW+Hxj/SSGKOJZmV
3P0AJvPQgkz9Y61vviQhODpy88aUaZWMxB9lgvSkUJo+Egc7pmU3sfK8XMT6GTVH
Nset/Au80YiU0LaJKKoV
=Kwwk
-----END PGP SIGNATURE-----
Merge tag 'renesas-intc-external-irq-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
From Simon Horman <horms+renesas@verge.net.au>:
Renesas INTC External IRQ pin driver
This provides two new INTC drivers for use with Renesas ARM-based SoCs and
makes use of them on the r8a7779 and sh73a0 SoCs.
It has been agreed by the relevant parties, Thomas Gleixner, Magnus Damm,
and myself that it would be best to merge this code through the renesas
tree and thus through the arm-soc tree.
This is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-v3.10
* tag 'renesas-intc-external-irq-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
irqchip: irqc: Add DT support
irqchip: intc-irqpin: Initial DT support
ARM: shmobile: Make r8a7779 INTC irqpin platform data static
ARM: shmobile: Make sh73a0 INTC irqpin platform data static
irqchip: Renesas IRQC driver
irqchip: intc-irqpin: GPL header for platform data
irqchip: intc-irqpin: Make use of devm functions
irqchip: intc-irqpin: Add force comments
irqchip: intc-irqpin: Cache mapped IRQ
irqchip: intc-irqpin: Whitespace fixes
ARM: shmobile: INTC External IRQ pin driver on r8a7779
ARM: shmobile: INTC External IRQ pin driver on sh73a0
ARM: shmobile: irq_pin() for static IRQ pin assignment
irqchip: Renesas INTC External IRQ pin driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Adjust the sh73a0 IRQ code to make use of the
INTC External IRQ pin driver for external
interrupt pins IRQ0 -> IRQ31.
This removes quite a bit of special-case code
in intc-sh73a0.c but the number of lines get
replaced with platform device information in
setup-sh73a0.c. The PFC code is also adjusted
to make gpio_to_irq() return the correct
interrupt number.
At this point the DT reference implementations
are not covered. In the future such code shall
tie in the INTC External IRQ pin driver via
DT, so this kind of verbose code is not needed
for the long term DT case.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7779 platforms now use the pinctrl API to control the INTC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the LBSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the USB pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the HSPI pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the SCIF pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The function is not documented in the r8a7779 datasheet. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7740 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7740 platforms now use the pinctrl API to control the LCD0 and
LCD1 pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the IrDA pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the USB pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the BSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the KEYSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinconf API to control pull-ups, the
corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the FSI pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the I2C pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the SCIFA and
SCIFB pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the LCD and
LCD2 pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh7372 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Only the CS pins and functions are currently handled.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add pin groups for the first two SDHI interfaces and two alternative pin
groups for the MMCIF interface on the r8a7740 SoC.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add pin groups for all three SDHI interfaces and two alternative pin
groups for the MMCIF interface on the sh7372 SoC.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tony Prisk