Commit Graph

1120 Commits

Author SHA1 Message Date
Linus Walleij fe0ec0ee07 pinctrl: capri: add dependency on OF
As this driver is using pinconf_generic_dt_node_to_map_pin() it
needs to depend on OF so as not to cause build problems on
archs that do not support OF.

Cc: Sherman Yin <syin@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-16 23:44:25 +01:00
Sherman Yin 54b1aa5a5b ARM: pinctrl: Add Broadcom Capri pinctrl driver
Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs.

v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig
    - make use of regmap
    - change CAPRI_PIN_UPDATE from macro to inline function.
    - Handle pull-up strength arg in Ohm instead of enum
v3: Re-work driver to be based on generic pin config. Moved config selection
    from Kconfig to bcm_defconfig.
v2: Use hyphens instead of underscore in DT property names.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Christian Daudt <bcm@fixthebug.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-16 14:25:38 +01:00
Srinivas Kandagatla c9dd66b73c pinctrl: st: Fix a typo in probe
Probe function had commas instead of semi-colons on some of the lines.
This patch just fixes those lines. No functional chagnes done in this
patch.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 13:59:51 +01:00
Linus Walleij 655dada627 pinctrl: sirf: lock IRQs when starting them
This uses the new API for tagging GPIO lines as in use by
IRQs. This enforces a few semantic checks on how the underlying
GPIO line is used.

Also assign the gpio_chip.dev pointer to be used for error
messages.

Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 13:59:44 +01:00
Barry Song b07ddcdcb2 pinctrl: sirf: put gpio interrupt pin into input status automatically
busses like i2c, spi and so on can parse the virq of their subnode automatically by
irq_of_parse_and_map(). for example, i2c will do that in of_i2c_register_devices().
people can put hwirq number attached to a gpio controller in dts, and drivers can
directly request the parsed virq.

for example, for an i2c client as below,
tangoc-ts@5c{
	compatible = "pixcir,tangoc-ts";
	interrupt-parent = <&gpio>;
	interrupts = <3 0>;
	reg = <0x5c>;
};
in i2c client probe(), it will request_irq(client->irq, ...) without
calling gpio_direction_input().
so here when we set irq type, we also put the pin to input direction.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 09:10:00 +01:00
Barry Song 8daeffb058 pinctrl: sirf: use only one irq_domain for the whole device node
in sirfsoc gpio probe(), we create 5 irq_domains for 5 gpio banks. but
in irq_create_of_mapping() of irqchip core level, irq_find_host() can
only return the 1st irq_domain attached the pinctrl dt device node as
we can see from the codes:

unsigned int irq_create_of_mapping(struct device_node *controller,
				   const u32 *intspec, unsigned int intsize)
{
	struct irq_domain *domain;
	...
	domain = controller ? irq_find_host(controller) : irq_default_domain;
}

struct irq_domain *irq_find_host(struct device_node *node)
{
	struct irq_domain *h, *found = NULL;
	int rc;

	/* We might want to match the legacy controller last since
	 * it might potentially be set to match all interrupts in
	 * the absence of a device node. This isn't a problem so far
	 * yet though...
	 */
	mutex_lock(&irq_domain_mutex);
	list_for_each_entry(h, &irq_domain_list, link) {
		if (h->ops->match)
			rc = h->ops->match(h, node);
		else
			rc = (h->of_node != NULL) && (h->of_node == node);

		if (rc) {
			found = h;
			break;
		}
	}
	mutex_unlock(&irq_domain_mutex);
	return found;
}

for sirfsoc, the 1st irq_domain attached to the device_node(controller) only
can do linear for the 1st 32 gpios. so for devices who use gpio hwirq above
32 and put the information in dt like:
                                tangoc-ts@5c{
                                        compatible = "pixcir,tangoc-ts";
+                                       interrupt-parent = <&gpio>;
+                                       interrupts = <34 0>;
                                };

we will fail to get the virq for these devices as hwirq will be bigger than
domain->revmap_data.linear.size in:
unsigned int irq_linear_revmap(struct irq_domain *domain,
			       irq_hw_number_t hwirq)
{

	/* Check revmap bounds; complain if exceeded */
	if (WARN_ON(hwirq >= domain->revmap_data.linear.size))
		return 0;

	return domain->revmap_data.linear.revmap[hwirq];
}

this patch drops redundant irq_domain and keep only one to fix the problem.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 09:07:56 +01:00
Tomi Valkeinen ad5d25fef8 pinctrl: single: fix infinite loop caused by bad mask
commit 4e7e8017a8 (pinctrl: pinctrl-single:
enhance to configure multiple pins of different modules) improved
support for pinctrl-single,bits option, but also caused a regression
in parsing badly configured mask data.

If the masks in DT data are not quite right,
pcs_parse_bits_in_pinctrl_entry() can end up in an infinite loop,
trashing memory at the same time.

Add a check to verify that each loop actually removes bits from the
'mask', so that the loop can eventually end.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 08:31:53 +01:00
Tomi Valkeinen dd4c2b3cb3 pinctrl: single: fix pcs_disable with bits_per_mux
pcs_enable() uses vals->mask instead of pcs->fmask when bits_per_mux is
enabled. However, pcs_disable() always uses pcs->fmask.

Fix pcs_disable() to use vals->mask with bits_per_mux.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 08:30:08 +01:00
Mallikarjun Kasoju f8720e5ec7 pinctrl: as3722: Set pin to output mode for some function
If pins are used for function output like pwm, clk32k,
power good etc then set it as output mode default.

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-14 10:34:18 +01:00
Rongjun Ying 8385af02ba pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync
USP0 has multiple functions, and has RX and TX frame sync signals,
for some scenarios like audio PCM, we don't need both of them.
so here we add two possibilities for USP0 only holding one of TX
and RX frame sync.

Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: Barry Song <Barry.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:51:10 +01:00
Bin Shi cbc3b873c8 pinctrl: sirf: fix the pins of sdmmc5 connected with TriG
sdmmc5 has only 3 pins CMD, CLK, DATA which are connected with CSR
TriG RF multi-GNSS. The hardware connection is like:
DATA -- GPS_SGN
CLK  -- GPS_RF_CLK
CMD  -- GPS_MAG
here we drop redundant pins in sdmmc5 group.

Signed-off-by: Bin Shi <Bin.Shi@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:50:21 +01:00
Qipan Li 6225633d71 pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6
commit af614b2301 adds lost USP-based UART pin groups for prima2,
but missed usp1_uart_nostreamctrl group for atlas6, this patch fixes it.

this makes USP(Universal Serial Ports) port1 can work as uart without
stream ctrl.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:48:38 +01:00
Chen-Yu Tsai b6a32a28cd pinctrl: sunxi: Add Allwinner A20 clock output pin functions
This patch adds the clock output pin functions on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:46:28 +01:00
Antonios Vamporakis a1edd49e42 pinctrl/lantiq: fix typo
Signed-off-by: Antonios Vamporakis <ant@area128.com>
CC: John Crispin <blogic@openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:13:38 +01:00
Valentine Barshak a5ffaf6445 pinctrl: sh-pfc: r8a7791: Add I2C pins
This adds I2C[0-4] pinmux support to R8A7791 SoC.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07 16:48:54 +01:00
Valentine Barshak 8e32c9671f pinctrl: sh-pfc: r8a7791: Add VIN pins
This adds VIN[0-2] pinmux support to r8a7791 SoC.
VIN1 B mirror is also added along with the primary
configuration since it's the only one that provides
access to all 24 data bits on VIN1.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07 16:48:50 +01:00
Valentine Barshak 5e5a298cdb pinctrl: sh-pfc: r8a7791: Group USB PWEN and OVC pins together
This groups USB PWEN and OVC pins together on R8A7791 SoC,
the same way it's done on R8A7790, since both are needed
for a USB device.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07 16:48:46 +01:00
Valentine Barshak 646ae3ef7e pinctrl: sh-pfc: r8a7790: Fix vsync value in the vin3_sync_mux array
This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/).

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07 16:48:35 +01:00
Laurent Pinchart 44a45b55a7 pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arrays
The arrays are never modified, declare them as const.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:28:40 +01:00
Laurent Pinchart f41a1efe63 pinctrl: sh-pfc: sh: Constify pins and cfg_regs arrays
The arrays are never modified, declare them as const.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:27:43 +01:00
Laurent Pinchart 6d5bddd525 pinctrl: sh-pfc: Constify IRQ GPIOs arrays
The arrays are never modified, make them const.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:26:54 +01:00
Laurent Pinchart 9aecff583e pinctrl: sh-pfc: Constify enum_ids and var_field_width compound literals
The enum_ids and var_field_width fields of struct pinmux_data_reg and
pinmux_cfg_reg are initialized using compound literals. Cast them to
const to store them in .rodata.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:25:59 +01:00
Axel Lin e476e77fe0 pinctrl: msm: Fix set gpio setting
Set g->out_bit bit for gpio output high, clear g->out_bit bit for gpio output
low.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 10:13:23 +01:00
Boris BREZILLON 37ef1d9243 pinctrl: at91: replace clk_prepare + clk_enable by clk_prepare_enable
Replace the clk_prepare and clk_enable calls by a single
clk_prepare_enable call.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 14:22:57 +01:00
Boris BREZILLON 795f9953ea pinctrl: at91: fix clk_unprepare and clk_disable order
clk_unprepare shall be called before clk_disable.
Fix the issue by replacing the clk_unprepare and clk_disable calls by a
single clk_disable_unprepare call.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 14:21:43 +01:00
Sherman Yin 8ba3f4d000 pinctrl: Adds slew-rate, input-enable/disable
This commit adds slew-rate and input-enable/disable support for pinconf
-generic.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:55:03 +01:00
Bjorn Andersson b31d100e92 pinctrl-msm: Rename compatible to be more specific
Use the more specific form 8974 for the compatible to reduce the
risk of future mishaps.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:33:42 +01:00
Bjorn Andersson 408e3c66da pinctrl-msm: Remove separate allocation of bitmaps
Make the bitmaps part of the msm_pinctrl allocation instead of
separately allocating them.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:32:50 +01:00
Bjorn Andersson f393e489c7 pinctrl-msm: Tidy up error handling
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:31:37 +01:00
Bjorn Andersson 1f2b239815 pinctrl-msm: Fix spelling misstakes and missing consts
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:30:25 +01:00
Bjorn Andersson 376f413a7d pinctrl: msm: Update Kconfig for PINCTRL_MSM8X74
Add GPIOLIB and OF as dependencies for PINCTRL_MSM8X74, to fix
build errors from i386-randconfig.
Also add help text and make the entries tristate, while touching
these entries.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
[Rebased on top of pin control development branch]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:29:25 +01:00
Alexandre Belloni b5728cf766 pinctrl: pinconf: remove warning: unused variable 'ops'
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-13 13:55:15 +01:00
Alexandre Belloni 4d9b8a8e46 pinctrl: at91: implement at91_pinconf_dbg_show
This allows to get the pin configuration by using debugfs. On my system:
 # cat /sys/kernel/debug/pinctrl/pinctrl.3/pinconf-pins

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-13 10:34:07 +01:00
Ashwini Ghuge 1a16bee6bc pinctrl: tegra: add pinmux controller driver for Tegra124
This adds a driver for the Tegra124 pinmux, and required
parameterization data for Tegra124.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra124-pinmux".

Originally written by Ashwini Gguhe.
Thierry:
 - Cleanups in patches.
ldewangan:
 - Fix some entries for groups.
 - Fix MUX enums and group sequence.

Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
CC: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:28:06 +01:00
Laurent Pinchart 70c8f01a35 sh-pfc: Support GPIO to IRQ mapping specified IRQ resources
On non-DT platforms IRQ controllers associated with the GPIOs have a
fixed IRQ base value known at compile time. The sh-pfc driver translates
GPIO number to IRQ numbers using a hardcoded table. This mechanism
breaks on DT platforms, as the IRQ base values are dynamic in that case.

Fix this by specifying IRQs associated with GPIOs in IRQ resources,
populated automatically from the device tree. When IRQ resources are
specified the driver requires one IRQ resource per GPIO able to generate
an interrupt, and uses the translation table to compute the IRQ resource
offset instead of the IRQ number.

Cc: devicetree@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:28 +01:00
Laurent Pinchart 5b46ac3a77 sh-pfc: Rename sh_pfc window field to windows
There's more than one window, name the field windows.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:23 +01:00
Laurent Pinchart de55c71feb sh-pfc: sh73a0: Sort IRQ entries by IRQ number
This makes catching duplicate entries easier. Merge the two IRQ9 entries
found after sorting.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:18 +01:00
Laurent Pinchart c48ca30341 sh-pfc: sh73a0: Add missing IRQ15
The external IRQ15 input multiplexed on GPIO 0 is missing. Add it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:12 +01:00
Laurent Pinchart 316b255001 sh-pfc: Terminate gpios array by -1
0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ
lists.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:06 +01:00
Laurent Pinchart 8d72a7fc8d sh-pfc: Turn unsigned indices into unsigned int
Some indices take positive values only, make them unsigned.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:06:49 +01:00
Alexandre Belloni c420619d51 pinctrl: pinconf: remove checks on ops->pin_config_get
ops->pin_config_get() is only used in one specific path that will only be taken
for generic pinconf drivers (ops->is_generic == true) when dumping the pinconf
by using debugfs.

By removing the check in pinconf_check_ops(), let's stop pressuring people to
write a pin_config_get() function that will never be used and so will probably
never be tested.

Removing the check in pinconf_pins_show() allows driver to not implement
pin_config_get() but still get a dump of the pinconf in debugfs by implementing
pin_config_dbg_show().

Finally, not implementing pin_config_get() now results in returning -ENOTSUPP
instead of -EINVAL. While this doesn't have any real impact for now, this feels
more right.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 19:11:07 +01:00
Alexandre Belloni 1292e69366 pinctrl: at91: initialize config parameter to 0
When passing a not initialized config parameter, at91_pinconf_get() would return
a bogus value. Fix that by initializing it to zero before using it.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 15:43:36 +01:00
Alexandre Belloni c2eb9e7f02 pinctrl: at91: correct a few typos
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 15:41:35 +01:00
Valentine Barshak 054d425909 pinctrl: sh-pfc: pfc-r8a7790: Add VIN2 and VIN3 pins
There are VIN2 and VIN3 channels available on the R8A7790 SoC.
VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit.
Add both here, covering all possible data pin configurations.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:39 +01:00
Valentine Barshak 317a03a9cb pinctrl: sh-pfc: pfc-r8a7790: Add missing VIN1 pins
Both VIN0 and VIN1 channels support identical input interfaces.
Add missing VIN1 pins here and organize them in the same pin
groups as VIN0.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:36 +01:00
Valentine Barshak 64fe8abc73 pinctrl: sh-pfc: pfc-r8a7790: Reorganize VIN0 data pins
This reorganizes and renames VIN0 data pin groups to cover
all possible configurations. There's total of eight data
pin groups, one per each configuration. Most of the groups
share the same pin/mux array. Only the 18-bit configuration
needs a separate pin/mux array since in combines interleaved
data pins.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:33 +01:00
Valentine Barshak a9e4c7bb46 pinctrl: sh-pfc: pfc-r8a7790: Group VIN0 HSYNC and VSYNC together
This groups VIN0 HSYNC and VSYNC pins together
since one cannot be used without another.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:30 +01:00
Valentine Barshak 7a57be873a pinctrl: sh-pfc: pfc-r8a7790: Rename VIN pin groups
This drops superfluous "signal" word from the pin group names
and renames data_enable group to clkenb as in the h/w manual.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:16 +01:00
Takashi Yoshii 2ef3967ef5 sh-pfc: r8a7791: Fix msiof groups to follow GROUP
SH_PFC_PIN_GROUP(), pins[], mux[], defines
 clk, sync, ss1, ss2, rx, tx
But, msiof?_groups[] defines
 clk, ctrl, data

Fix msiof[012]_groups members to be consistent to PIN_GROUP.

Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10 16:22:55 +01:00
Kuninori Morimoto fcec5b2254 sh-pfc: r8a7790: Add Audio pin support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10 16:22:54 +01:00