Masahiro Yamada 3f6e698604 mtd: rawnand: denali_dt: set clk_x_rate to 200 MHz unconditionally ... Since commit 1bb8866677 ("mtd: nand: denali: handle timing parameters by setup_data_interface()"), denali_dt.c gets the clock rate from the clock driver. The driver expects the frequency of the bus interface clock, whereas the clock driver of SOCFPGA provides the core clock. Thus, the setup_data_interface() hook calculates timing parameters based on a wrong frequency. To make it work without relying on the clock driver, hard-code the clock frequency, 200MHz. This is fine for existing DT of UniPhier, and also fixes the issue of SOCFPGA because both platforms use 200 MHz for the bus interface clock. Fixes: 1bb8866677 ("mtd: nand: denali: handle timing parameters by setup_data_interface()") Cc: linux-stable <stable@vger.kernel.org> #4.14+ Reported-by: Philipp Rosenberger <p.rosenberger@linutronix.de> Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Richard Weinberger <richard@nod.at> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>		2018-06-22 18:47:56 +02:00
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onenand	treewide: kzalloc() -> kcalloc()	2018-06-12 16:19:22 -07:00
raw	mtd: rawnand: denali_dt: set clk_x_rate to 200 MHz unconditionally	2018-06-22 18:47:56 +02:00
Kconfig	mtd: Move onenand code base to drivers/mtd/nand/onenand	2018-03-15 15:40:37 +01:00
Makefile	mtd: Move onenand code base to drivers/mtd/nand/onenand	2018-03-15 15:40:37 +01:00
bbt.c	mtd: nand: Add core infrastructure to deal with NAND devices	2018-02-16 10:10:53 +01:00
core.c	mtd: nand: Fix nanddev_mtd_erase()	2018-04-22 19:59:29 +02:00