534 lines
13 KiB
C
534 lines
13 KiB
C
#include "drmP.h"
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#include "nouveau_drv.h"
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#include <linux/pagemap.h>
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#include <linux/slab.h>
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#define NV_CTXDMA_PAGE_SHIFT 12
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#define NV_CTXDMA_PAGE_SIZE (1 << NV_CTXDMA_PAGE_SHIFT)
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#define NV_CTXDMA_PAGE_MASK (NV_CTXDMA_PAGE_SIZE - 1)
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struct nouveau_sgdma_be {
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struct ttm_backend backend;
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struct drm_device *dev;
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dma_addr_t *pages;
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bool *ttm_alloced;
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unsigned nr_pages;
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u64 offset;
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bool bound;
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};
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static int
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nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages,
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struct page **pages, struct page *dummy_read_page,
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dma_addr_t *dma_addrs)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_device *dev = nvbe->dev;
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NV_DEBUG(nvbe->dev, "num_pages = %ld\n", num_pages);
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if (nvbe->pages)
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return -EINVAL;
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nvbe->pages = kmalloc(sizeof(dma_addr_t) * num_pages, GFP_KERNEL);
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if (!nvbe->pages)
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return -ENOMEM;
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nvbe->ttm_alloced = kmalloc(sizeof(bool) * num_pages, GFP_KERNEL);
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if (!nvbe->ttm_alloced)
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return -ENOMEM;
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nvbe->nr_pages = 0;
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while (num_pages--) {
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if (dma_addrs[nvbe->nr_pages] != DMA_ERROR_CODE) {
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nvbe->pages[nvbe->nr_pages] =
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dma_addrs[nvbe->nr_pages];
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nvbe->ttm_alloced[nvbe->nr_pages] = true;
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} else {
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nvbe->pages[nvbe->nr_pages] =
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pci_map_page(dev->pdev, pages[nvbe->nr_pages], 0,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev,
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nvbe->pages[nvbe->nr_pages])) {
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be->func->clear(be);
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return -EFAULT;
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}
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}
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nvbe->nr_pages++;
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}
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return 0;
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}
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static void
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nouveau_sgdma_clear(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_device *dev;
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if (nvbe && nvbe->pages) {
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dev = nvbe->dev;
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NV_DEBUG(dev, "\n");
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if (nvbe->bound)
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be->func->unbind(be);
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while (nvbe->nr_pages--) {
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if (!nvbe->ttm_alloced[nvbe->nr_pages])
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pci_unmap_page(dev->pdev, nvbe->pages[nvbe->nr_pages],
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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}
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kfree(nvbe->pages);
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kfree(nvbe->ttm_alloced);
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nvbe->pages = NULL;
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nvbe->ttm_alloced = NULL;
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nvbe->nr_pages = 0;
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}
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}
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static void
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nouveau_sgdma_destroy(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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if (be) {
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NV_DEBUG(nvbe->dev, "\n");
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if (nvbe) {
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if (nvbe->pages)
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be->func->clear(be);
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kfree(nvbe);
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}
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}
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}
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static int
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nv04_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_device *dev = nvbe->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
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unsigned i, j, pte;
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NV_DEBUG(dev, "pg=0x%lx\n", mem->start);
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nvbe->offset = mem->start << PAGE_SHIFT;
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pte = (nvbe->offset >> NV_CTXDMA_PAGE_SHIFT) + 2;
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for (i = 0; i < nvbe->nr_pages; i++) {
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dma_addr_t dma_offset = nvbe->pages[i];
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uint32_t offset_l = lower_32_bits(dma_offset);
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for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++, pte++) {
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nv_wo32(gpuobj, (pte * 4) + 0, offset_l | 3);
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dma_offset += NV_CTXDMA_PAGE_SIZE;
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}
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}
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nvbe->bound = true;
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return 0;
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}
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static int
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nv04_sgdma_unbind(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_device *dev = nvbe->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
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unsigned i, j, pte;
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NV_DEBUG(dev, "\n");
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if (!nvbe->bound)
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return 0;
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pte = (nvbe->offset >> NV_CTXDMA_PAGE_SHIFT) + 2;
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for (i = 0; i < nvbe->nr_pages; i++) {
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for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++, pte++)
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nv_wo32(gpuobj, (pte * 4) + 0, 0x00000000);
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}
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nvbe->bound = false;
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return 0;
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}
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static struct ttm_backend_func nv04_sgdma_backend = {
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.populate = nouveau_sgdma_populate,
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.clear = nouveau_sgdma_clear,
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.bind = nv04_sgdma_bind,
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.unbind = nv04_sgdma_unbind,
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.destroy = nouveau_sgdma_destroy
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};
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static void
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nv41_sgdma_flush(struct nouveau_sgdma_be *nvbe)
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{
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struct drm_device *dev = nvbe->dev;
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nv_wr32(dev, 0x100810, 0x00000022);
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if (!nv_wait(dev, 0x100810, 0x00000100, 0x00000100))
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NV_ERROR(dev, "vm flush timeout: 0x%08x\n",
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nv_rd32(dev, 0x100810));
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nv_wr32(dev, 0x100810, 0x00000000);
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}
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static int
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nv41_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
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dma_addr_t *list = nvbe->pages;
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u32 pte = mem->start << 2;
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u32 cnt = nvbe->nr_pages;
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nvbe->offset = mem->start << PAGE_SHIFT;
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while (cnt--) {
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nv_wo32(pgt, pte, (*list++ >> 7) | 1);
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pte += 4;
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}
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nv41_sgdma_flush(nvbe);
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nvbe->bound = true;
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return 0;
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}
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static int
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nv41_sgdma_unbind(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
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u32 pte = (nvbe->offset >> 12) << 2;
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u32 cnt = nvbe->nr_pages;
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while (cnt--) {
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nv_wo32(pgt, pte, 0x00000000);
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pte += 4;
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}
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nv41_sgdma_flush(nvbe);
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nvbe->bound = false;
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return 0;
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}
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static struct ttm_backend_func nv41_sgdma_backend = {
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.populate = nouveau_sgdma_populate,
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.clear = nouveau_sgdma_clear,
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.bind = nv41_sgdma_bind,
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.unbind = nv41_sgdma_unbind,
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.destroy = nouveau_sgdma_destroy
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};
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static void
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nv44_sgdma_flush(struct nouveau_sgdma_be *nvbe)
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{
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struct drm_device *dev = nvbe->dev;
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nv_wr32(dev, 0x100814, (nvbe->nr_pages - 1) << 12);
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nv_wr32(dev, 0x100808, nvbe->offset | 0x20);
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if (!nv_wait(dev, 0x100808, 0x00000001, 0x00000001))
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NV_ERROR(dev, "gart flush timeout: 0x%08x\n",
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nv_rd32(dev, 0x100808));
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nv_wr32(dev, 0x100808, 0x00000000);
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}
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static void
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nv44_sgdma_fill(struct nouveau_gpuobj *pgt, dma_addr_t *list, u32 base, u32 cnt)
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{
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struct drm_nouveau_private *dev_priv = pgt->dev->dev_private;
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dma_addr_t dummy = dev_priv->gart_info.dummy.addr;
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u32 pte, tmp[4];
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pte = base >> 2;
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base &= ~0x0000000f;
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tmp[0] = nv_ro32(pgt, base + 0x0);
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tmp[1] = nv_ro32(pgt, base + 0x4);
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tmp[2] = nv_ro32(pgt, base + 0x8);
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tmp[3] = nv_ro32(pgt, base + 0xc);
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while (cnt--) {
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u32 addr = list ? (*list++ >> 12) : (dummy >> 12);
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switch (pte++ & 0x3) {
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case 0:
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tmp[0] &= ~0x07ffffff;
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tmp[0] |= addr;
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break;
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case 1:
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tmp[0] &= ~0xf8000000;
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tmp[0] |= addr << 27;
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tmp[1] &= ~0x003fffff;
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tmp[1] |= addr >> 5;
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break;
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case 2:
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tmp[1] &= ~0xffc00000;
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tmp[1] |= addr << 22;
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tmp[2] &= ~0x0001ffff;
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tmp[2] |= addr >> 10;
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break;
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case 3:
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tmp[2] &= ~0xfffe0000;
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tmp[2] |= addr << 17;
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tmp[3] &= ~0x00000fff;
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tmp[3] |= addr >> 15;
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break;
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}
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}
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tmp[3] |= 0x40000000;
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nv_wo32(pgt, base + 0x0, tmp[0]);
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nv_wo32(pgt, base + 0x4, tmp[1]);
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nv_wo32(pgt, base + 0x8, tmp[2]);
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nv_wo32(pgt, base + 0xc, tmp[3]);
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}
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static int
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nv44_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
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dma_addr_t *list = nvbe->pages;
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u32 pte = mem->start << 2, tmp[4];
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u32 cnt = nvbe->nr_pages;
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int i;
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nvbe->offset = mem->start << PAGE_SHIFT;
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if (pte & 0x0000000c) {
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u32 max = 4 - ((pte >> 2) & 0x3);
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u32 part = (cnt > max) ? max : cnt;
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nv44_sgdma_fill(pgt, list, pte, part);
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pte += (part << 2);
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list += part;
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cnt -= part;
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}
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while (cnt >= 4) {
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for (i = 0; i < 4; i++)
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tmp[i] = *list++ >> 12;
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nv_wo32(pgt, pte + 0x0, tmp[0] >> 0 | tmp[1] << 27);
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nv_wo32(pgt, pte + 0x4, tmp[1] >> 5 | tmp[2] << 22);
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nv_wo32(pgt, pte + 0x8, tmp[2] >> 10 | tmp[3] << 17);
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nv_wo32(pgt, pte + 0xc, tmp[3] >> 15 | 0x40000000);
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pte += 0x10;
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cnt -= 4;
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}
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if (cnt)
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nv44_sgdma_fill(pgt, list, pte, cnt);
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nv44_sgdma_flush(nvbe);
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nvbe->bound = true;
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return 0;
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}
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static int
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nv44_sgdma_unbind(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
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u32 pte = (nvbe->offset >> 12) << 2;
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u32 cnt = nvbe->nr_pages;
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if (pte & 0x0000000c) {
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u32 max = 4 - ((pte >> 2) & 0x3);
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u32 part = (cnt > max) ? max : cnt;
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nv44_sgdma_fill(pgt, NULL, pte, part);
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pte += (part << 2);
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cnt -= part;
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}
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while (cnt >= 4) {
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nv_wo32(pgt, pte + 0x0, 0x00000000);
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nv_wo32(pgt, pte + 0x4, 0x00000000);
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nv_wo32(pgt, pte + 0x8, 0x00000000);
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nv_wo32(pgt, pte + 0xc, 0x00000000);
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pte += 0x10;
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cnt -= 4;
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}
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if (cnt)
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nv44_sgdma_fill(pgt, NULL, pte, cnt);
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nv44_sgdma_flush(nvbe);
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nvbe->bound = false;
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return 0;
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}
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static struct ttm_backend_func nv44_sgdma_backend = {
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.populate = nouveau_sgdma_populate,
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.clear = nouveau_sgdma_clear,
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.bind = nv44_sgdma_bind,
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.unbind = nv44_sgdma_unbind,
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.destroy = nouveau_sgdma_destroy
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};
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static int
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nv50_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct nouveau_mem *node = mem->mm_node;
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/* noop: bound in move_notify() */
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node->pages = nvbe->pages;
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nvbe->pages = (dma_addr_t *)node;
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nvbe->bound = true;
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return 0;
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}
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static int
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nv50_sgdma_unbind(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct nouveau_mem *node = (struct nouveau_mem *)nvbe->pages;
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/* noop: unbound in move_notify() */
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nvbe->pages = node->pages;
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node->pages = NULL;
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nvbe->bound = false;
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return 0;
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}
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static struct ttm_backend_func nv50_sgdma_backend = {
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.populate = nouveau_sgdma_populate,
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.clear = nouveau_sgdma_clear,
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.bind = nv50_sgdma_bind,
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.unbind = nv50_sgdma_unbind,
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.destroy = nouveau_sgdma_destroy
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};
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struct ttm_backend *
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nouveau_sgdma_init_ttm(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_sgdma_be *nvbe;
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nvbe = kzalloc(sizeof(*nvbe), GFP_KERNEL);
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if (!nvbe)
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return NULL;
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nvbe->dev = dev;
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nvbe->backend.func = dev_priv->gart_info.func;
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return &nvbe->backend;
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}
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int
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nouveau_sgdma_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = NULL;
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u32 aper_size, align;
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int ret;
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if (dev_priv->card_type >= NV_40 && drm_pci_device_is_pcie(dev))
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aper_size = 512 * 1024 * 1024;
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else
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aper_size = 64 * 1024 * 1024;
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/* Dear NVIDIA, NV44+ would like proper present bits in PTEs for
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* christmas. The cards before it have them, the cards after
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* it have them, why is NV44 so unloved?
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*/
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dev_priv->gart_info.dummy.page = alloc_page(GFP_DMA32 | GFP_KERNEL);
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if (!dev_priv->gart_info.dummy.page)
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return -ENOMEM;
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dev_priv->gart_info.dummy.addr =
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pci_map_page(dev->pdev, dev_priv->gart_info.dummy.page,
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0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev, dev_priv->gart_info.dummy.addr)) {
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NV_ERROR(dev, "error mapping dummy page\n");
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__free_page(dev_priv->gart_info.dummy.page);
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dev_priv->gart_info.dummy.page = NULL;
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return -ENOMEM;
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}
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if (dev_priv->card_type >= NV_50) {
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dev_priv->gart_info.aper_base = 0;
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dev_priv->gart_info.aper_size = aper_size;
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dev_priv->gart_info.type = NOUVEAU_GART_HW;
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dev_priv->gart_info.func = &nv50_sgdma_backend;
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} else
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if (drm_pci_device_is_pcie(dev) &&
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dev_priv->chipset > 0x40 && dev_priv->chipset != 0x45) {
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if (nv44_graph_class(dev)) {
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dev_priv->gart_info.func = &nv44_sgdma_backend;
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align = 512 * 1024;
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} else {
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dev_priv->gart_info.func = &nv41_sgdma_backend;
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align = 16;
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}
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ret = nouveau_gpuobj_new(dev, NULL, aper_size / 1024, align,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &gpuobj);
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if (ret) {
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NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
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return ret;
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}
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dev_priv->gart_info.sg_ctxdma = gpuobj;
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dev_priv->gart_info.aper_base = 0;
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dev_priv->gart_info.aper_size = aper_size;
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dev_priv->gart_info.type = NOUVEAU_GART_HW;
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} else {
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ret = nouveau_gpuobj_new(dev, NULL, (aper_size / 1024) + 8, 16,
|
|
NVOBJ_FLAG_ZERO_ALLOC |
|
|
NVOBJ_FLAG_ZERO_FREE, &gpuobj);
|
|
if (ret) {
|
|
NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
nv_wo32(gpuobj, 0, NV_CLASS_DMA_IN_MEMORY |
|
|
(1 << 12) /* PT present */ |
|
|
(0 << 13) /* PT *not* linear */ |
|
|
(0 << 14) /* RW */ |
|
|
(2 << 16) /* PCI */);
|
|
nv_wo32(gpuobj, 4, aper_size - 1);
|
|
|
|
dev_priv->gart_info.sg_ctxdma = gpuobj;
|
|
dev_priv->gart_info.aper_base = 0;
|
|
dev_priv->gart_info.aper_size = aper_size;
|
|
dev_priv->gart_info.type = NOUVEAU_GART_PDMA;
|
|
dev_priv->gart_info.func = &nv04_sgdma_backend;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
nouveau_sgdma_takedown(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
nouveau_gpuobj_ref(NULL, &dev_priv->gart_info.sg_ctxdma);
|
|
|
|
if (dev_priv->gart_info.dummy.page) {
|
|
pci_unmap_page(dev->pdev, dev_priv->gart_info.dummy.addr,
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
__free_page(dev_priv->gart_info.dummy.page);
|
|
dev_priv->gart_info.dummy.page = NULL;
|
|
}
|
|
}
|
|
|
|
uint32_t
|
|
nouveau_sgdma_get_physical(struct drm_device *dev, uint32_t offset)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
|
|
int pte = (offset >> NV_CTXDMA_PAGE_SHIFT) + 2;
|
|
|
|
BUG_ON(dev_priv->card_type >= NV_50);
|
|
|
|
return (nv_ro32(gpuobj, 4 * pte) & ~NV_CTXDMA_PAGE_MASK) |
|
|
(offset & NV_CTXDMA_PAGE_MASK);
|
|
}
|