194 lines
5.7 KiB
C
194 lines
5.7 KiB
C
/*
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* bfin_sport.h - interface to Blackfin SPORTs
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*
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __BFIN_SPORT_H__
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#define __BFIN_SPORT_H__
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/* Sport mode: it can be set to TDM, i2s or others */
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#define NORM_MODE 0x0
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#define TDM_MODE 0x1
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#define I2S_MODE 0x2
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/* Data format, normal, a-law or u-law */
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#define NORM_FORMAT 0x0
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#define ALAW_FORMAT 0x2
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#define ULAW_FORMAT 0x3
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/* Function driver which use sport must initialize the structure */
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struct sport_config {
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/* TDM (multichannels), I2S or other mode */
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unsigned int mode:3;
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/* if TDM mode is selected, channels must be set */
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int channels; /* Must be in 8 units */
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unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
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/* I2S mode */
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unsigned int right_first:1; /* Right stereo channel first */
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/* In mormal mode, the following item need to be set */
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unsigned int lsb_first:1; /* order of transmit or receive data */
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unsigned int fsync:1; /* Frame sync required */
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unsigned int data_indep:1; /* data independent frame sync generated */
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unsigned int act_low:1; /* Active low TFS */
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unsigned int late_fsync:1; /* Late frame sync */
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unsigned int tckfe:1;
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unsigned int sec_en:1; /* Secondary side enabled */
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/* Choose clock source */
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unsigned int int_clk:1; /* Internal or external clock */
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/* If external clock is used, the following fields are ignored */
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int serial_clk;
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int fsync_clk;
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unsigned int data_format:2; /* Normal, u-law or a-law */
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int word_len; /* How length of the word in bits, 3-32 bits */
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int dma_enabled;
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};
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/* Userspace interface */
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#define SPORT_IOC_MAGIC 'P'
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#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
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#ifdef __KERNEL__
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#include <linux/types.h>
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/*
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* All Blackfin system MMRs are padded to 32bits even if the register
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* itself is only 16bits. So use a helper macro to streamline this.
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*/
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#define __BFP(m) u16 m; u16 __pad_##m
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struct sport_register {
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__BFP(tcr1);
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__BFP(tcr2);
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__BFP(tclkdiv);
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__BFP(tfsdiv);
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union {
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u32 tx32;
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u16 tx16;
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};
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u32 __pad_tx;
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union {
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u32 rx32; /* use the anomaly wrapper below */
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u16 rx16;
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};
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u32 __pad_rx;
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__BFP(rcr1);
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__BFP(rcr2);
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__BFP(rclkdiv);
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__BFP(rfsdiv);
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__BFP(stat);
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__BFP(chnl);
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__BFP(mcmc1);
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__BFP(mcmc2);
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u32 mtcs0;
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u32 mtcs1;
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u32 mtcs2;
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u32 mtcs3;
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u32 mrcs0;
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u32 mrcs1;
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u32 mrcs2;
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u32 mrcs3;
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};
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#undef __BFP
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struct bfin_snd_platform_data {
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const unsigned short *pin_req;
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};
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#define bfin_read_sport_rx32(base) \
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({ \
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struct sport_register *__mmrs = (void *)base; \
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u32 __ret; \
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unsigned long flags; \
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if (ANOMALY_05000473) \
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local_irq_save(flags); \
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__ret = __mmrs->rx32; \
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if (ANOMALY_05000473) \
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local_irq_restore(flags); \
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__ret; \
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})
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#endif
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/* SPORT_TCR1 Masks */
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#define TSPEN 0x0001 /* TX enable */
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#define ITCLK 0x0002 /* Internal TX Clock Select */
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#define TDTYPE 0x000C /* TX Data Formatting Select */
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#define DTYPE_NORM 0x0000 /* Data Format Normal */
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#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
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#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
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#define TLSBIT 0x0010 /* TX Bit Order */
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#define ITFS 0x0200 /* Internal TX Frame Sync Select */
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#define TFSR 0x0400 /* TX Frame Sync Required Select */
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#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
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#define LTFS 0x1000 /* Low TX Frame Sync Select */
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#define LATFS 0x2000 /* Late TX Frame Sync Select */
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#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
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/* SPORT_TCR2 Masks */
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#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
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#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
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#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
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#define TXSE 0x0100 /* TX Secondary Enable */
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#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
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#define TRFST 0x0400 /* TX Right-First Data Order */
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/* SPORT_RCR1 Masks */
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#define RSPEN 0x0001 /* RX enable */
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#define IRCLK 0x0002 /* Internal RX Clock Select */
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#define RDTYPE 0x000C /* RX Data Formatting Select */
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/* DTYPE_* defined above */
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#define RLSBIT 0x0010 /* RX Bit Order */
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#define IRFS 0x0200 /* Internal RX Frame Sync Select */
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#define RFSR 0x0400 /* RX Frame Sync Required Select */
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#define LRFS 0x1000 /* Low RX Frame Sync Select */
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#define LARFS 0x2000 /* Late RX Frame Sync Select */
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#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
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/* SPORT_RCR2 Masks */
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/* SLEN defined above */
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#define RXSE 0x0100 /* RX Secondary Enable */
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#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
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#define RRFST 0x0400 /* Right-First Data Order */
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/* SPORT_STAT Masks */
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#define RXNE 0x0001 /* RX FIFO Not Empty Status */
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#define RUVF 0x0002 /* RX Underflow Status */
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#define ROVF 0x0004 /* RX Overflow Status */
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#define TXF 0x0008 /* TX FIFO Full Status */
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#define TUVF 0x0010 /* TX Underflow Status */
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#define TOVF 0x0020 /* TX Overflow Status */
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#define TXHRE 0x0040 /* TX Hold Register Empty */
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/* SPORT_MCMC1 Masks */
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#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
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#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
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#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
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#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
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#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
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#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
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/* SPORT_MCMC2 Masks */
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#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
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#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
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#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
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#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
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#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
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#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
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#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
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#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
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#define MFD 0xF000 /* Multichannel Frame Delay */
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#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
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#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
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#endif
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