280 lines
8.2 KiB
C
280 lines
8.2 KiB
C
/*
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* arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#if defined(EBIU_SDGCTL)
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#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
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defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
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defined(CONFIG_MEM_MT48LC32M8A2_75) || \
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defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
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defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC32M8A2_75)
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#if (CONFIG_SCLK_HZ > 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_7
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#define SDRAM_tRAS_num 7
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_6
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#define SDRAM_tRAS_num 6
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_5
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#define SDRAM_tRAS_num 5
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_2
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#define SDRAM_tRAS_num 2
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ <= 29850746)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_1
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#define SDRAM_tRAS_num 1
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#endif
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/*
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* The BF526-EZ-Board changed SDRAM chips between revisions,
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* so we use below timings to accommodate both.
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*/
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#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
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#if (CONFIG_SCLK_HZ > 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_8
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#define SDRAM_tRAS_num 8
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_7
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#define SDRAM_tRAS_num 7
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_6
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#define SDRAM_tRAS_num 6
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_5
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#define SDRAM_tRAS_num 5
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ <= 29850746)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_2
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#define SDRAM_tRAS_num 2
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#endif
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#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
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defined(CONFIG_MEM_MT48LC8M32B2B5_7)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
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defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
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defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC32M8A2_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_2
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#endif
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#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
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/* Equation from section 17 (p17-46) of BF533 HRM */
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#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
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/* Enable SCLK Out */
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#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
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#else
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#define mem_SDRRC CONFIG_MEM_SDRRC
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#define mem_SDGCTL CONFIG_MEM_SDGCTL
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#endif
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#endif
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#if defined(EBIU_DDRCTL0)
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#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
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#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
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#define DDR_CLK_HZ(x) (1000*1000*1000/x)
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#if defined(CONFIG_MEM_MT46V32M16_6T)
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#define DDR_SIZE DEVSZ_512
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#define DDR_WIDTH DEVWD_16
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#define DDR_MAX_tCK 13
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#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
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#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
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#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
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#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
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#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
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#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
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#define DDR_tWTR DDR_TWTR(1)
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#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
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#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
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#endif
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#if defined(CONFIG_MEM_MT46V32M16_5B)
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#define DDR_SIZE DEVSZ_512
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#define DDR_WIDTH DEVWD_16
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#define DDR_MAX_tCK 13
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#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
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#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
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#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
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#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
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#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
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#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
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#define DDR_tWTR DDR_TWTR(2)
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#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
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#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
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#endif
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#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
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# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
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#elif(CONFIG_SCLK_HZ <= 133333333)
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# define DDR_CL CL_2
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#else
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# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
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#endif
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#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
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#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
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#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
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| DDR_tMRD | DDR_tWR | DDR_tRCD)
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#define mem_DDRCTL2 DDR_CL
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#else
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#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
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#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
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#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
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#endif
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#endif
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#if defined CONFIG_CLKIN_HALF
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#define CLKIN_HALF 1
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#else
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#define CLKIN_HALF 0
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#endif
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#if defined CONFIG_PLL_BYPASS
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#define PLL_BYPASS 1
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#else
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#define PLL_BYPASS 0
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#endif
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