1593 lines
40 KiB
C
1593 lines
40 KiB
C
/*
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* Support functions for OMAP GPIO
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*
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* Copyright (C) 2003-2005 Nokia Corporation
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* Written by Juha Yrjölä <juha.yrjola@nokia.com>
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/syscore_ops.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <mach/irqs.h>
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#include <mach/gpio.h>
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#include <asm/mach/irq.h>
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struct gpio_bank {
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unsigned long pbase;
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void __iomem *base;
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u16 irq;
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u16 virtual_irq_start;
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int method;
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#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
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u32 suspend_wakeup;
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u32 saved_wakeup;
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#endif
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u32 non_wakeup_gpios;
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u32 enabled_non_wakeup_gpios;
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u32 saved_datain;
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u32 saved_fallingdetect;
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u32 saved_risingdetect;
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u32 level_mask;
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u32 toggle_mask;
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spinlock_t lock;
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struct gpio_chip chip;
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struct clk *dbck;
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u32 mod_usage;
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u32 dbck_enable_mask;
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struct device *dev;
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bool dbck_flag;
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int stride;
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u32 width;
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void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
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struct omap_gpio_reg_offs *regs;
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};
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#ifdef CONFIG_ARCH_OMAP3
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struct omap3_gpio_regs {
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u32 irqenable1;
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u32 irqenable2;
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u32 wake_en;
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u32 ctrl;
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u32 oe;
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u32 leveldetect0;
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u32 leveldetect1;
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u32 risingdetect;
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u32 fallingdetect;
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u32 dataout;
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};
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static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
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#endif
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/*
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* TODO: Cleanup gpio_bank usage as it is having information
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* related to all instances of the device
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*/
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static struct gpio_bank *gpio_bank;
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/* TODO: Analyze removing gpio_bank_count usage from driver code */
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int gpio_bank_count;
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#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
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#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
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static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
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{
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void __iomem *reg = bank->base;
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u32 l;
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reg += bank->regs->direction;
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l = __raw_readl(reg);
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if (is_input)
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l |= 1 << gpio;
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else
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l &= ~(1 << gpio);
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__raw_writel(l, reg);
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}
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/* set data out value using dedicate set/clear register */
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static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
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{
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void __iomem *reg = bank->base;
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u32 l = GPIO_BIT(bank, gpio);
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if (enable)
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reg += bank->regs->set_dataout;
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else
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reg += bank->regs->clr_dataout;
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__raw_writel(l, reg);
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}
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/* set data out value using mask register */
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static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
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{
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void __iomem *reg = bank->base + bank->regs->dataout;
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u32 gpio_bit = GPIO_BIT(bank, gpio);
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u32 l;
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l = __raw_readl(reg);
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if (enable)
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l |= gpio_bit;
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else
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l &= ~gpio_bit;
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__raw_writel(l, reg);
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}
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static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
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{
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void __iomem *reg = bank->base + bank->regs->datain;
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return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
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}
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static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
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{
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void __iomem *reg = bank->base + bank->regs->dataout;
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return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
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}
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#define MOD_REG_BIT(reg, bit_mask, set) \
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do { \
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int l = __raw_readl(base + reg); \
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if (set) l |= bit_mask; \
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else l &= ~bit_mask; \
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__raw_writel(l, base + reg); \
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} while(0)
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/**
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* _set_gpio_debounce - low level gpio debounce time
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* @bank: the gpio bank we're acting upon
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* @gpio: the gpio number on this @gpio
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* @debounce: debounce time to use
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*
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* OMAP's debounce time is in 31us steps so we need
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* to convert and round up to the closest unit.
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*/
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static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
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unsigned debounce)
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{
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void __iomem *reg;
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u32 val;
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u32 l;
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if (!bank->dbck_flag)
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return;
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if (debounce < 32)
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debounce = 0x01;
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else if (debounce > 7936)
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debounce = 0xff;
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else
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debounce = (debounce / 0x1f) - 1;
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l = GPIO_BIT(bank, gpio);
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reg = bank->base + bank->regs->debounce;
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__raw_writel(debounce, reg);
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reg = bank->base + bank->regs->debounce_en;
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val = __raw_readl(reg);
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if (debounce) {
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val |= l;
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clk_enable(bank->dbck);
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} else {
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val &= ~l;
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clk_disable(bank->dbck);
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}
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bank->dbck_enable_mask = val;
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__raw_writel(val, reg);
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}
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#ifdef CONFIG_ARCH_OMAP2PLUS
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static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
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int trigger)
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{
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void __iomem *base = bank->base;
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u32 gpio_bit = 1 << gpio;
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if (cpu_is_omap44xx()) {
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MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
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trigger & IRQ_TYPE_LEVEL_LOW);
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MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
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trigger & IRQ_TYPE_LEVEL_HIGH);
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MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
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trigger & IRQ_TYPE_EDGE_RISING);
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MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
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trigger & IRQ_TYPE_EDGE_FALLING);
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} else {
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MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
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trigger & IRQ_TYPE_LEVEL_LOW);
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MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
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trigger & IRQ_TYPE_LEVEL_HIGH);
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MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
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trigger & IRQ_TYPE_EDGE_RISING);
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MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
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trigger & IRQ_TYPE_EDGE_FALLING);
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}
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if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
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if (cpu_is_omap44xx()) {
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MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
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trigger != 0);
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} else {
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/*
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* GPIO wakeup request can only be generated on edge
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* transitions
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*/
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if (trigger & IRQ_TYPE_EDGE_BOTH)
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__raw_writel(1 << gpio, bank->base
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+ OMAP24XX_GPIO_SETWKUENA);
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else
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__raw_writel(1 << gpio, bank->base
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+ OMAP24XX_GPIO_CLEARWKUENA);
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}
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}
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/* This part needs to be executed always for OMAP{34xx, 44xx} */
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if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
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(bank->non_wakeup_gpios & gpio_bit)) {
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/*
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* Log the edge gpio and manually trigger the IRQ
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* after resume if the input level changes
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* to avoid irq lost during PER RET/OFF mode
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* Applies for omap2 non-wakeup gpio and all omap3 gpios
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*/
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if (trigger & IRQ_TYPE_EDGE_BOTH)
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bank->enabled_non_wakeup_gpios |= gpio_bit;
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else
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bank->enabled_non_wakeup_gpios &= ~gpio_bit;
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}
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if (cpu_is_omap44xx()) {
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bank->level_mask =
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__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
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__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
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} else {
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bank->level_mask =
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__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
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__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
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}
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP1
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/*
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* This only applies to chips that can't do both rising and falling edge
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* detection at once. For all other chips, this function is a noop.
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*/
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static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
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{
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void __iomem *reg = bank->base;
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u32 l = 0;
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switch (bank->method) {
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
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break;
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#ifdef CONFIG_ARCH_OMAP15XX
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case METHOD_GPIO_1510:
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reg += OMAP1510_GPIO_INT_CONTROL;
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break;
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#endif
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#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
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case METHOD_GPIO_7XX:
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reg += OMAP7XX_GPIO_INT_CONTROL;
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break;
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#endif
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default:
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return;
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}
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l = __raw_readl(reg);
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if ((l >> gpio) & 1)
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l &= ~(1 << gpio);
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else
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l |= 1 << gpio;
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__raw_writel(l, reg);
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}
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#endif
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static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
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{
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void __iomem *reg = bank->base;
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u32 l = 0;
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switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
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l = __raw_readl(reg);
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if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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bank->toggle_mask |= 1 << gpio;
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if (trigger & IRQ_TYPE_EDGE_RISING)
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l |= 1 << gpio;
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else if (trigger & IRQ_TYPE_EDGE_FALLING)
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l &= ~(1 << gpio);
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else
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goto bad;
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break;
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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case METHOD_GPIO_1510:
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reg += OMAP1510_GPIO_INT_CONTROL;
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l = __raw_readl(reg);
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if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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bank->toggle_mask |= 1 << gpio;
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if (trigger & IRQ_TYPE_EDGE_RISING)
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l |= 1 << gpio;
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else if (trigger & IRQ_TYPE_EDGE_FALLING)
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l &= ~(1 << gpio);
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else
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goto bad;
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break;
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#endif
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#ifdef CONFIG_ARCH_OMAP16XX
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case METHOD_GPIO_1610:
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if (gpio & 0x08)
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reg += OMAP1610_GPIO_EDGE_CTRL2;
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else
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reg += OMAP1610_GPIO_EDGE_CTRL1;
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gpio &= 0x07;
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l = __raw_readl(reg);
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l &= ~(3 << (gpio << 1));
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if (trigger & IRQ_TYPE_EDGE_RISING)
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l |= 2 << (gpio << 1);
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if (trigger & IRQ_TYPE_EDGE_FALLING)
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l |= 1 << (gpio << 1);
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if (trigger)
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/* Enable wake-up during idle for dynamic tick */
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__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
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else
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__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
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break;
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#endif
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#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
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case METHOD_GPIO_7XX:
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reg += OMAP7XX_GPIO_INT_CONTROL;
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l = __raw_readl(reg);
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if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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bank->toggle_mask |= 1 << gpio;
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if (trigger & IRQ_TYPE_EDGE_RISING)
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l |= 1 << gpio;
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else if (trigger & IRQ_TYPE_EDGE_FALLING)
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l &= ~(1 << gpio);
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else
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goto bad;
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break;
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#endif
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#ifdef CONFIG_ARCH_OMAP2PLUS
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case METHOD_GPIO_24XX:
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case METHOD_GPIO_44XX:
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set_24xx_gpio_triggering(bank, gpio, trigger);
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return 0;
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#endif
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default:
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goto bad;
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}
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__raw_writel(l, reg);
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return 0;
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bad:
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return -EINVAL;
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}
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static int gpio_irq_type(struct irq_data *d, unsigned type)
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{
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struct gpio_bank *bank;
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unsigned gpio;
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int retval;
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unsigned long flags;
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if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
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gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
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else
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gpio = d->irq - IH_GPIO_BASE;
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if (type & ~IRQ_TYPE_SENSE_MASK)
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return -EINVAL;
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/* OMAP1 allows only only edge triggering */
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if (!cpu_class_is_omap2()
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&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
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return -EINVAL;
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bank = irq_data_get_irq_chip_data(d);
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spin_lock_irqsave(&bank->lock, flags);
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retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
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spin_unlock_irqrestore(&bank->lock, flags);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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return retval;
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}
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static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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{
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void __iomem *reg = bank->base;
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reg += bank->regs->irqstatus;
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__raw_writel(gpio_mask, reg);
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/* Workaround for clearing DSP GPIO interrupts to allow retention */
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if (bank->regs->irqstatus2) {
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reg = bank->base + bank->regs->irqstatus2;
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__raw_writel(gpio_mask, reg);
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}
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/* Flush posted write for the irq status to avoid spurious interrupts */
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__raw_readl(reg);
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}
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|
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static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
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{
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_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
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}
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|
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static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
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{
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void __iomem *reg = bank->base;
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u32 l;
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u32 mask = (1 << bank->width) - 1;
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reg += bank->regs->irqenable;
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l = __raw_readl(reg);
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if (bank->regs->irqenable_inv)
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l = ~l;
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l &= mask;
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return l;
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}
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|
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static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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{
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void __iomem *reg = bank->base;
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u32 l;
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if (bank->regs->set_irqenable) {
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reg += bank->regs->set_irqenable;
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l = gpio_mask;
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} else {
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reg += bank->regs->irqenable;
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l = __raw_readl(reg);
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if (bank->regs->irqenable_inv)
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l &= ~gpio_mask;
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else
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l |= gpio_mask;
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}
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__raw_writel(l, reg);
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}
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|
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static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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{
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void __iomem *reg = bank->base;
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u32 l;
|
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|
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if (bank->regs->clr_irqenable) {
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reg += bank->regs->clr_irqenable;
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l = gpio_mask;
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} else {
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reg += bank->regs->irqenable;
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l = __raw_readl(reg);
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if (bank->regs->irqenable_inv)
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l |= gpio_mask;
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else
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l &= ~gpio_mask;
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}
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|
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__raw_writel(l, reg);
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}
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|
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static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
|
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{
|
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_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
|
|
}
|
|
|
|
/*
|
|
* Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
|
|
* 1510 does not seem to have a wake-up register. If JTAG is connected
|
|
* to the target, system will wake up always on GPIO events. While
|
|
* system is running all registered GPIO interrupts need to have wake-up
|
|
* enabled. When system is suspended, only selected GPIO interrupts need
|
|
* to have wake-up enabled.
|
|
*/
|
|
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
|
|
{
|
|
u32 gpio_bit = GPIO_BIT(bank, gpio);
|
|
unsigned long flags;
|
|
|
|
if (bank->non_wakeup_gpios & gpio_bit) {
|
|
dev_err(bank->dev,
|
|
"Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
if (enable)
|
|
bank->suspend_wakeup |= gpio_bit;
|
|
else
|
|
bank->suspend_wakeup &= ~gpio_bit;
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void _reset_gpio(struct gpio_bank *bank, int gpio)
|
|
{
|
|
_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
|
|
}
|
|
|
|
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
|
|
static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
|
|
{
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
struct gpio_bank *bank;
|
|
int retval;
|
|
|
|
bank = irq_data_get_irq_chip_data(d);
|
|
retval = _set_gpio_wakeup(bank, gpio, enable);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
/* Set trigger to none. You need to enable the desired trigger with
|
|
* request_irq() or set_irq_type().
|
|
*/
|
|
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
|
if (bank->method == METHOD_GPIO_1510) {
|
|
void __iomem *reg;
|
|
|
|
/* Claim the pin for MPU */
|
|
reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
|
|
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
|
|
}
|
|
#endif
|
|
if (!cpu_class_is_omap1()) {
|
|
if (!bank->mod_usage) {
|
|
void __iomem *reg = bank->base;
|
|
u32 ctrl;
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
|
reg += OMAP24XX_GPIO_CTRL;
|
|
else if (cpu_is_omap44xx())
|
|
reg += OMAP4_GPIO_CTRL;
|
|
ctrl = __raw_readl(reg);
|
|
/* Module is enabled, clocks are not gated */
|
|
ctrl &= 0xFFFFFFFE;
|
|
__raw_writel(ctrl, reg);
|
|
}
|
|
bank->mod_usage |= 1 << offset;
|
|
}
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
if (bank->method == METHOD_GPIO_1610) {
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
__raw_writel(1 << offset, reg);
|
|
}
|
|
#endif
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
if (bank->method == METHOD_GPIO_24XX) {
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
__raw_writel(1 << offset, reg);
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
if (bank->method == METHOD_GPIO_44XX) {
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
__raw_writel(1 << offset, reg);
|
|
}
|
|
#endif
|
|
if (!cpu_class_is_omap1()) {
|
|
bank->mod_usage &= ~(1 << offset);
|
|
if (!bank->mod_usage) {
|
|
void __iomem *reg = bank->base;
|
|
u32 ctrl;
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
|
reg += OMAP24XX_GPIO_CTRL;
|
|
else if (cpu_is_omap44xx())
|
|
reg += OMAP4_GPIO_CTRL;
|
|
ctrl = __raw_readl(reg);
|
|
/* Module is disabled, clocks are gated */
|
|
ctrl |= 1;
|
|
__raw_writel(ctrl, reg);
|
|
}
|
|
}
|
|
_reset_gpio(bank, bank->chip.base + offset);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
|
|
/*
|
|
* We need to unmask the GPIO bank interrupt as soon as possible to
|
|
* avoid missing GPIO interrupts for other lines in the bank.
|
|
* Then we need to mask-read-clear-unmask the triggered GPIO lines
|
|
* in the bank to avoid missing nested interrupts for a GPIO line.
|
|
* If we wait to unmask individual GPIO lines in the bank after the
|
|
* line's interrupt handler has been run, we may miss some nested
|
|
* interrupts.
|
|
*/
|
|
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
void __iomem *isr_reg = NULL;
|
|
u32 isr;
|
|
unsigned int gpio_irq, gpio_index;
|
|
struct gpio_bank *bank;
|
|
u32 retrigger = 0;
|
|
int unmasked = 0;
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
bank = irq_get_handler_data(irq);
|
|
isr_reg = bank->base + bank->regs->irqstatus;
|
|
|
|
if (WARN_ON(!isr_reg))
|
|
goto exit;
|
|
|
|
while(1) {
|
|
u32 isr_saved, level_mask = 0;
|
|
u32 enabled;
|
|
|
|
enabled = _get_gpio_irqbank_mask(bank);
|
|
isr_saved = isr = __raw_readl(isr_reg) & enabled;
|
|
|
|
if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
|
|
isr &= 0x0000ffff;
|
|
|
|
if (cpu_class_is_omap2()) {
|
|
level_mask = bank->level_mask & enabled;
|
|
}
|
|
|
|
/* clear edge sensitive interrupts before handler(s) are
|
|
called so that we don't miss any interrupt occurred while
|
|
executing them */
|
|
_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
|
|
_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
|
|
_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
|
|
|
|
/* if there is only edge sensitive GPIO pin interrupts
|
|
configured, we could unmask GPIO bank interrupt immediately */
|
|
if (!level_mask && !unmasked) {
|
|
unmasked = 1;
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
isr |= retrigger;
|
|
retrigger = 0;
|
|
if (!isr)
|
|
break;
|
|
|
|
gpio_irq = bank->virtual_irq_start;
|
|
for (; isr != 0; isr >>= 1, gpio_irq++) {
|
|
gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
|
|
|
|
if (!(isr & 1))
|
|
continue;
|
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
/*
|
|
* Some chips can't respond to both rising and falling
|
|
* at the same time. If this irq was requested with
|
|
* both flags, we need to flip the ICR data for the IRQ
|
|
* to respond to the IRQ for the opposite direction.
|
|
* This will be indicated in the bank toggle_mask.
|
|
*/
|
|
if (bank->toggle_mask & (1 << gpio_index))
|
|
_toggle_gpio_edge_triggering(bank, gpio_index);
|
|
#endif
|
|
|
|
generic_handle_irq(gpio_irq);
|
|
}
|
|
}
|
|
/* if bank has any level sensitive GPIO pin interrupt
|
|
configured, we must unmask the bank interrupt only after
|
|
handler(s) are executed in order to avoid spurious bank
|
|
interrupt */
|
|
exit:
|
|
if (!unmasked)
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static void gpio_irq_shutdown(struct irq_data *d)
|
|
{
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
_reset_gpio(bank, gpio);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
|
|
static void gpio_ack_irq(struct irq_data *d)
|
|
{
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
}
|
|
|
|
static void gpio_mask_irq(struct irq_data *d)
|
|
{
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
|
|
static void gpio_unmask_irq(struct irq_data *d)
|
|
{
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
unsigned int irq_mask = GPIO_BIT(bank, gpio);
|
|
u32 trigger = irqd_get_trigger_type(d);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
if (trigger)
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
|
|
|
|
/* For level-triggered GPIOs, the clearing must be done after
|
|
* the HW source is cleared, thus after the handler has run */
|
|
if (bank->level_mask & irq_mask) {
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
}
|
|
|
|
_set_gpio_irqenable(bank, gpio, 1);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
|
|
static struct irq_chip gpio_irq_chip = {
|
|
.name = "GPIO",
|
|
.irq_shutdown = gpio_irq_shutdown,
|
|
.irq_ack = gpio_ack_irq,
|
|
.irq_mask = gpio_mask_irq,
|
|
.irq_unmask = gpio_unmask_irq,
|
|
.irq_set_type = gpio_irq_type,
|
|
.irq_set_wake = gpio_wake_enable,
|
|
};
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
#include <linux/platform_device.h>
|
|
|
|
static int omap_mpuio_suspend_noirq(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
void __iomem *mask_reg = bank->base +
|
|
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
bank->saved_wakeup = __raw_readl(mask_reg);
|
|
__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_mpuio_resume_noirq(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
void __iomem *mask_reg = bank->base +
|
|
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
__raw_writel(bank->saved_wakeup, mask_reg);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
|
|
.suspend_noirq = omap_mpuio_suspend_noirq,
|
|
.resume_noirq = omap_mpuio_resume_noirq,
|
|
};
|
|
|
|
/* use platform_driver for this. */
|
|
static struct platform_driver omap_mpuio_driver = {
|
|
.driver = {
|
|
.name = "mpuio",
|
|
.pm = &omap_mpuio_dev_pm_ops,
|
|
},
|
|
};
|
|
|
|
static struct platform_device omap_mpuio_device = {
|
|
.name = "mpuio",
|
|
.id = -1,
|
|
.dev = {
|
|
.driver = &omap_mpuio_driver.driver,
|
|
}
|
|
/* could list the /proc/iomem resources */
|
|
};
|
|
|
|
static inline void mpuio_init(void)
|
|
{
|
|
struct gpio_bank *bank = &gpio_bank[0];
|
|
platform_set_drvdata(&omap_mpuio_device, bank);
|
|
|
|
if (platform_driver_register(&omap_mpuio_driver) == 0)
|
|
(void) platform_device_register(&omap_mpuio_device);
|
|
}
|
|
|
|
#else
|
|
static inline void mpuio_init(void) {}
|
|
#endif /* 16xx */
|
|
|
|
#else
|
|
|
|
#define bank_is_mpuio(bank) 0
|
|
static inline void mpuio_init(void) {}
|
|
|
|
#endif
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
/* REVISIT these are stupid implementations! replace by ones that
|
|
* don't switch on METHOD_* and which mostly avoid spinlocks
|
|
*/
|
|
|
|
static int gpio_input(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct gpio_bank *bank;
|
|
unsigned long flags;
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
_set_gpio_direction(bank, offset, 1);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
static int gpio_is_input(struct gpio_bank *bank, int mask)
|
|
{
|
|
void __iomem *reg = bank->base + bank->regs->direction;
|
|
|
|
return __raw_readl(reg) & mask;
|
|
}
|
|
|
|
static int gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct gpio_bank *bank;
|
|
void __iomem *reg;
|
|
int gpio;
|
|
u32 mask;
|
|
|
|
gpio = chip->base + offset;
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
reg = bank->base;
|
|
mask = GPIO_BIT(bank, gpio);
|
|
|
|
if (gpio_is_input(bank, mask))
|
|
return _get_gpio_datain(bank, gpio);
|
|
else
|
|
return _get_gpio_dataout(bank, gpio);
|
|
}
|
|
|
|
static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
|
|
{
|
|
struct gpio_bank *bank;
|
|
unsigned long flags;
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
bank->set_dataout(bank, offset, value);
|
|
_set_gpio_direction(bank, offset, 0);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
|
|
unsigned debounce)
|
|
{
|
|
struct gpio_bank *bank;
|
|
unsigned long flags;
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
if (!bank->dbck) {
|
|
bank->dbck = clk_get(bank->dev, "dbclk");
|
|
if (IS_ERR(bank->dbck))
|
|
dev_err(bank->dev, "Could not get gpio dbck\n");
|
|
}
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
_set_gpio_debounce(bank, offset, debounce);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|
{
|
|
struct gpio_bank *bank;
|
|
unsigned long flags;
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
bank->set_dataout(bank, offset, value);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
|
|
static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct gpio_bank *bank;
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
return bank->virtual_irq_start + offset;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
static void __init omap_gpio_show_rev(struct gpio_bank *bank)
|
|
{
|
|
static bool called;
|
|
u32 rev;
|
|
|
|
if (called || bank->regs->revision == USHRT_MAX)
|
|
return;
|
|
|
|
rev = __raw_readw(bank->base + bank->regs->revision);
|
|
pr_info("OMAP GPIO hardware version %d.%d\n",
|
|
(rev >> 4) & 0x0f, rev & 0x0f);
|
|
|
|
called = true;
|
|
}
|
|
|
|
/* This lock class tells lockdep that GPIO irqs are in a different
|
|
* category than their parents, so it won't report false recursion.
|
|
*/
|
|
static struct lock_class_key gpio_lock_class;
|
|
|
|
static inline int init_gpio_info(struct platform_device *pdev)
|
|
{
|
|
/* TODO: Analyze removing gpio_bank_count usage from driver code */
|
|
gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
|
|
GFP_KERNEL);
|
|
if (!gpio_bank) {
|
|
dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
|
|
return -ENOMEM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* TODO: Cleanup cpu_is_* checks */
|
|
static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
|
|
{
|
|
if (cpu_class_is_omap2()) {
|
|
if (cpu_is_omap44xx()) {
|
|
__raw_writel(0xffffffff, bank->base +
|
|
OMAP4_GPIO_IRQSTATUSCLR0);
|
|
__raw_writel(0x00000000, bank->base +
|
|
OMAP4_GPIO_DEBOUNCENABLE);
|
|
/* Initialize interface clk ungated, module enabled */
|
|
__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
|
|
} else if (cpu_is_omap34xx()) {
|
|
__raw_writel(0x00000000, bank->base +
|
|
OMAP24XX_GPIO_IRQENABLE1);
|
|
__raw_writel(0xffffffff, bank->base +
|
|
OMAP24XX_GPIO_IRQSTATUS1);
|
|
__raw_writel(0x00000000, bank->base +
|
|
OMAP24XX_GPIO_DEBOUNCE_EN);
|
|
|
|
/* Initialize interface clk ungated, module enabled */
|
|
__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
|
|
} else if (cpu_is_omap24xx()) {
|
|
static const u32 non_wakeup_gpios[] = {
|
|
0xe203ffc0, 0x08700040
|
|
};
|
|
if (id < ARRAY_SIZE(non_wakeup_gpios))
|
|
bank->non_wakeup_gpios = non_wakeup_gpios[id];
|
|
}
|
|
} else if (cpu_class_is_omap1()) {
|
|
if (bank_is_mpuio(bank))
|
|
__raw_writew(0xffff, bank->base +
|
|
OMAP_MPUIO_GPIO_MASKIT / bank->stride);
|
|
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
|
|
__raw_writew(0xffff, bank->base
|
|
+ OMAP1510_GPIO_INT_MASK);
|
|
__raw_writew(0x0000, bank->base
|
|
+ OMAP1510_GPIO_INT_STATUS);
|
|
}
|
|
if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
|
|
__raw_writew(0x0000, bank->base
|
|
+ OMAP1610_GPIO_IRQENABLE1);
|
|
__raw_writew(0xffff, bank->base
|
|
+ OMAP1610_GPIO_IRQSTATUS1);
|
|
__raw_writew(0x0014, bank->base
|
|
+ OMAP1610_GPIO_SYSCONFIG);
|
|
|
|
/*
|
|
* Enable system clock for GPIO module.
|
|
* The CAM_CLK_CTRL *is* really the right place.
|
|
*/
|
|
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
|
|
ULPD_CAM_CLK_CTRL);
|
|
}
|
|
if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
|
|
__raw_writel(0xffffffff, bank->base
|
|
+ OMAP7XX_GPIO_INT_MASK);
|
|
__raw_writel(0x00000000, bank->base
|
|
+ OMAP7XX_GPIO_INT_STATUS);
|
|
}
|
|
}
|
|
}
|
|
|
|
static __init void
|
|
omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
|
|
unsigned int num)
|
|
{
|
|
struct irq_chip_generic *gc;
|
|
struct irq_chip_type *ct;
|
|
|
|
gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
|
|
handle_simple_irq);
|
|
ct = gc->chip_types;
|
|
|
|
/* NOTE: No ack required, reading IRQ status clears it. */
|
|
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
|
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
|
ct->chip.irq_set_type = gpio_irq_type;
|
|
/* REVISIT: assuming only 16xx supports MPUIO wake events */
|
|
if (cpu_is_omap16xx())
|
|
ct->chip.irq_set_wake = gpio_wake_enable,
|
|
|
|
ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
|
|
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
|
|
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
|
}
|
|
|
|
static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
|
|
{
|
|
int j;
|
|
static int gpio;
|
|
|
|
bank->mod_usage = 0;
|
|
/*
|
|
* REVISIT eventually switch from OMAP-specific gpio structs
|
|
* over to the generic ones
|
|
*/
|
|
bank->chip.request = omap_gpio_request;
|
|
bank->chip.free = omap_gpio_free;
|
|
bank->chip.direction_input = gpio_input;
|
|
bank->chip.get = gpio_get;
|
|
bank->chip.direction_output = gpio_output;
|
|
bank->chip.set_debounce = gpio_debounce;
|
|
bank->chip.set = gpio_set;
|
|
bank->chip.to_irq = gpio_2irq;
|
|
if (bank_is_mpuio(bank)) {
|
|
bank->chip.label = "mpuio";
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
bank->chip.dev = &omap_mpuio_device.dev;
|
|
#endif
|
|
bank->chip.base = OMAP_MPUIO(0);
|
|
} else {
|
|
bank->chip.label = "gpio";
|
|
bank->chip.base = gpio;
|
|
gpio += bank->width;
|
|
}
|
|
bank->chip.ngpio = bank->width;
|
|
|
|
gpiochip_add(&bank->chip);
|
|
|
|
for (j = bank->virtual_irq_start;
|
|
j < bank->virtual_irq_start + bank->width; j++) {
|
|
irq_set_lockdep_class(j, &gpio_lock_class);
|
|
irq_set_chip_data(j, bank);
|
|
if (bank_is_mpuio(bank)) {
|
|
omap_mpuio_alloc_gc(bank, j, bank->width);
|
|
} else {
|
|
irq_set_chip(j, &gpio_irq_chip);
|
|
irq_set_handler(j, handle_simple_irq);
|
|
set_irq_flags(j, IRQF_VALID);
|
|
}
|
|
}
|
|
irq_set_chained_handler(bank->irq, gpio_irq_handler);
|
|
irq_set_handler_data(bank->irq, bank);
|
|
}
|
|
|
|
static int __devinit omap_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
static int gpio_init_done;
|
|
struct omap_gpio_platform_data *pdata;
|
|
struct resource *res;
|
|
int id;
|
|
struct gpio_bank *bank;
|
|
|
|
if (!pdev->dev.platform_data)
|
|
return -EINVAL;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
|
|
if (!gpio_init_done) {
|
|
int ret;
|
|
|
|
ret = init_gpio_info(pdev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
id = pdev->id;
|
|
bank = &gpio_bank[id];
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (unlikely(!res)) {
|
|
dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
|
|
return -ENODEV;
|
|
}
|
|
|
|
bank->irq = res->start;
|
|
bank->virtual_irq_start = pdata->virtual_irq_start;
|
|
bank->method = pdata->bank_type;
|
|
bank->dev = &pdev->dev;
|
|
bank->dbck_flag = pdata->dbck_flag;
|
|
bank->stride = pdata->bank_stride;
|
|
bank->width = pdata->bank_width;
|
|
|
|
bank->regs = pdata->regs;
|
|
|
|
if (bank->regs->set_dataout && bank->regs->clr_dataout)
|
|
bank->set_dataout = _set_gpio_dataout_reg;
|
|
else
|
|
bank->set_dataout = _set_gpio_dataout_mask;
|
|
|
|
spin_lock_init(&bank->lock);
|
|
|
|
/* Static mapping, never released */
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (unlikely(!res)) {
|
|
dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
|
|
return -ENODEV;
|
|
}
|
|
|
|
bank->base = ioremap(res->start, resource_size(res));
|
|
if (!bank->base) {
|
|
dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pm_runtime_enable(bank->dev);
|
|
pm_runtime_get_sync(bank->dev);
|
|
|
|
omap_gpio_mod_init(bank, id);
|
|
omap_gpio_chip_init(bank);
|
|
omap_gpio_show_rev(bank);
|
|
|
|
if (!gpio_init_done)
|
|
gpio_init_done = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
|
static int omap_gpio_suspend(void)
|
|
{
|
|
int i;
|
|
|
|
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
|
|
return 0;
|
|
|
|
for (i = 0; i < gpio_bank_count; i++) {
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
void __iomem *wake_status;
|
|
void __iomem *wake_clear;
|
|
void __iomem *wake_set;
|
|
unsigned long flags;
|
|
|
|
switch (bank->method) {
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
case METHOD_GPIO_1610:
|
|
wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
|
|
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
|
|
break;
|
|
#endif
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
case METHOD_GPIO_24XX:
|
|
wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
|
|
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
case METHOD_GPIO_44XX:
|
|
wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
break;
|
|
#endif
|
|
default:
|
|
continue;
|
|
}
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
bank->saved_wakeup = __raw_readl(wake_status);
|
|
__raw_writel(0xffffffff, wake_clear);
|
|
__raw_writel(bank->suspend_wakeup, wake_set);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_gpio_resume(void)
|
|
{
|
|
int i;
|
|
|
|
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
|
|
return;
|
|
|
|
for (i = 0; i < gpio_bank_count; i++) {
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
void __iomem *wake_clear;
|
|
void __iomem *wake_set;
|
|
unsigned long flags;
|
|
|
|
switch (bank->method) {
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
case METHOD_GPIO_1610:
|
|
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
|
|
break;
|
|
#endif
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
case METHOD_GPIO_24XX:
|
|
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
case METHOD_GPIO_44XX:
|
|
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
break;
|
|
#endif
|
|
default:
|
|
continue;
|
|
}
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
__raw_writel(0xffffffff, wake_clear);
|
|
__raw_writel(bank->saved_wakeup, wake_set);
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
}
|
|
|
|
static struct syscore_ops omap_gpio_syscore_ops = {
|
|
.suspend = omap_gpio_suspend,
|
|
.resume = omap_gpio_resume,
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
|
|
|
static int workaround_enabled;
|
|
|
|
void omap2_gpio_prepare_for_idle(int off_mode)
|
|
{
|
|
int i, c = 0;
|
|
int min = 0;
|
|
|
|
if (cpu_is_omap34xx())
|
|
min = 1;
|
|
|
|
for (i = min; i < gpio_bank_count; i++) {
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
u32 l1 = 0, l2 = 0;
|
|
int j;
|
|
|
|
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
|
|
clk_disable(bank->dbck);
|
|
|
|
if (!off_mode)
|
|
continue;
|
|
|
|
/* If going to OFF, remove triggering for all
|
|
* non-wakeup GPIOs. Otherwise spurious IRQs will be
|
|
* generated. See OMAP2420 Errata item 1.101. */
|
|
if (!(bank->enabled_non_wakeup_gpios))
|
|
continue;
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
bank->saved_datain = __raw_readl(bank->base +
|
|
OMAP24XX_GPIO_DATAIN);
|
|
l1 = __raw_readl(bank->base +
|
|
OMAP24XX_GPIO_FALLINGDETECT);
|
|
l2 = __raw_readl(bank->base +
|
|
OMAP24XX_GPIO_RISINGDETECT);
|
|
}
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
bank->saved_datain = __raw_readl(bank->base +
|
|
OMAP4_GPIO_DATAIN);
|
|
l1 = __raw_readl(bank->base +
|
|
OMAP4_GPIO_FALLINGDETECT);
|
|
l2 = __raw_readl(bank->base +
|
|
OMAP4_GPIO_RISINGDETECT);
|
|
}
|
|
|
|
bank->saved_fallingdetect = l1;
|
|
bank->saved_risingdetect = l2;
|
|
l1 &= ~bank->enabled_non_wakeup_gpios;
|
|
l2 &= ~bank->enabled_non_wakeup_gpios;
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
__raw_writel(l1, bank->base +
|
|
OMAP24XX_GPIO_FALLINGDETECT);
|
|
__raw_writel(l2, bank->base +
|
|
OMAP24XX_GPIO_RISINGDETECT);
|
|
}
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
|
|
__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
|
|
}
|
|
|
|
c++;
|
|
}
|
|
if (!c) {
|
|
workaround_enabled = 0;
|
|
return;
|
|
}
|
|
workaround_enabled = 1;
|
|
}
|
|
|
|
void omap2_gpio_resume_after_idle(void)
|
|
{
|
|
int i;
|
|
int min = 0;
|
|
|
|
if (cpu_is_omap34xx())
|
|
min = 1;
|
|
for (i = min; i < gpio_bank_count; i++) {
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
u32 l = 0, gen, gen0, gen1;
|
|
int j;
|
|
|
|
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
|
|
clk_enable(bank->dbck);
|
|
|
|
if (!workaround_enabled)
|
|
continue;
|
|
|
|
if (!(bank->enabled_non_wakeup_gpios))
|
|
continue;
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
__raw_writel(bank->saved_fallingdetect,
|
|
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
__raw_writel(bank->saved_risingdetect,
|
|
bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
|
|
}
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
__raw_writel(bank->saved_fallingdetect,
|
|
bank->base + OMAP4_GPIO_FALLINGDETECT);
|
|
__raw_writel(bank->saved_risingdetect,
|
|
bank->base + OMAP4_GPIO_RISINGDETECT);
|
|
l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
|
|
}
|
|
|
|
/* Check if any of the non-wakeup interrupt GPIOs have changed
|
|
* state. If so, generate an IRQ by software. This is
|
|
* horribly racy, but it's the best we can do to work around
|
|
* this silicon bug. */
|
|
l ^= bank->saved_datain;
|
|
l &= bank->enabled_non_wakeup_gpios;
|
|
|
|
/*
|
|
* No need to generate IRQs for the rising edge for gpio IRQs
|
|
* configured with falling edge only; and vice versa.
|
|
*/
|
|
gen0 = l & bank->saved_fallingdetect;
|
|
gen0 &= bank->saved_datain;
|
|
|
|
gen1 = l & bank->saved_risingdetect;
|
|
gen1 &= ~(bank->saved_datain);
|
|
|
|
/* FIXME: Consider GPIO IRQs with level detections properly! */
|
|
gen = l & (~(bank->saved_fallingdetect) &
|
|
~(bank->saved_risingdetect));
|
|
/* Consider all GPIO IRQs needed to be updated */
|
|
gen |= gen0 | gen1;
|
|
|
|
if (gen) {
|
|
u32 old0, old1;
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
old0 = __raw_readl(bank->base +
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
|
old1 = __raw_readl(bank->base +
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
|
__raw_writel(old0 | gen, bank->base +
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
|
__raw_writel(old1 | gen, bank->base +
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
|
__raw_writel(old0, bank->base +
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
|
__raw_writel(old1, bank->base +
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
|
}
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
old0 = __raw_readl(bank->base +
|
|
OMAP4_GPIO_LEVELDETECT0);
|
|
old1 = __raw_readl(bank->base +
|
|
OMAP4_GPIO_LEVELDETECT1);
|
|
__raw_writel(old0 | l, bank->base +
|
|
OMAP4_GPIO_LEVELDETECT0);
|
|
__raw_writel(old1 | l, bank->base +
|
|
OMAP4_GPIO_LEVELDETECT1);
|
|
__raw_writel(old0, bank->base +
|
|
OMAP4_GPIO_LEVELDETECT0);
|
|
__raw_writel(old1, bank->base +
|
|
OMAP4_GPIO_LEVELDETECT1);
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
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#ifdef CONFIG_ARCH_OMAP3
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/* save the registers of bank 2-6 */
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|
void omap_gpio_save_context(void)
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|
{
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int i;
|
|
|
|
/* saving banks from 2-6 only since GPIO1 is in WKUP */
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for (i = 1; i < gpio_bank_count; i++) {
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struct gpio_bank *bank = &gpio_bank[i];
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gpio_context[i].irqenable1 =
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__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
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gpio_context[i].irqenable2 =
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__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
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|
gpio_context[i].wake_en =
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
|
|
gpio_context[i].ctrl =
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
|
|
gpio_context[i].oe =
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_OE);
|
|
gpio_context[i].leveldetect0 =
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
|
|
gpio_context[i].leveldetect1 =
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
gpio_context[i].risingdetect =
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
gpio_context[i].fallingdetect =
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
gpio_context[i].dataout =
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
|
|
}
|
|
}
|
|
|
|
/* restore the required registers of bank 2-6 */
|
|
void omap_gpio_restore_context(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 1; i < gpio_bank_count; i++) {
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
__raw_writel(gpio_context[i].irqenable1,
|
|
bank->base + OMAP24XX_GPIO_IRQENABLE1);
|
|
__raw_writel(gpio_context[i].irqenable2,
|
|
bank->base + OMAP24XX_GPIO_IRQENABLE2);
|
|
__raw_writel(gpio_context[i].wake_en,
|
|
bank->base + OMAP24XX_GPIO_WAKE_EN);
|
|
__raw_writel(gpio_context[i].ctrl,
|
|
bank->base + OMAP24XX_GPIO_CTRL);
|
|
__raw_writel(gpio_context[i].oe,
|
|
bank->base + OMAP24XX_GPIO_OE);
|
|
__raw_writel(gpio_context[i].leveldetect0,
|
|
bank->base + OMAP24XX_GPIO_LEVELDETECT0);
|
|
__raw_writel(gpio_context[i].leveldetect1,
|
|
bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
__raw_writel(gpio_context[i].risingdetect,
|
|
bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
__raw_writel(gpio_context[i].fallingdetect,
|
|
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
__raw_writel(gpio_context[i].dataout,
|
|
bank->base + OMAP24XX_GPIO_DATAOUT);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static struct platform_driver omap_gpio_driver = {
|
|
.probe = omap_gpio_probe,
|
|
.driver = {
|
|
.name = "omap_gpio",
|
|
},
|
|
};
|
|
|
|
/*
|
|
* gpio driver register needs to be done before
|
|
* machine_init functions access gpio APIs.
|
|
* Hence omap_gpio_drv_reg() is a postcore_initcall.
|
|
*/
|
|
static int __init omap_gpio_drv_reg(void)
|
|
{
|
|
return platform_driver_register(&omap_gpio_driver);
|
|
}
|
|
postcore_initcall(omap_gpio_drv_reg);
|
|
|
|
static int __init omap_gpio_sysinit(void)
|
|
{
|
|
mpuio_init();
|
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
|
if (cpu_is_omap16xx() || cpu_class_is_omap2())
|
|
register_syscore_ops(&omap_gpio_syscore_ops);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(omap_gpio_sysinit);
|