591 lines
14 KiB
C
591 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2003-2008 Simtec Electronics
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// Ben Dooks <ben@simtec.co.uk>
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//
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// http://www.simtec.co.uk/products/EB2410ITX/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/syscore_ops.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/platform_device.h>
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#include <linux/dm9000.h>
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#include <linux/ata_platform.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/serial_8250.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_data/asoc-s3c24xx_simtec.h>
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#include <linux/platform_data/hwmon-s3c.h>
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#include <linux/platform_data/i2c-s3c2410.h>
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#include <linux/platform_data/mtd-nand-s3c2410.h>
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#include <net/ax88796.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach-types.h>
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#include <mach/fb.h>
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#include <mach/hardware.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-lcd.h>
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#include <mach/gpio-samsung.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq.h>
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#include <plat/devs.h>
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#include <plat/gpio-cfg.h>
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#include <plat/samsung-time.h>
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#include "bast.h"
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#include "common.h"
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#include "simtec.h"
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#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
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/* macros for virtual address mods for the io space entries */
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#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
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#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
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#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
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#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
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/* macros to modify the physical addresses for io space */
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#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
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#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
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#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
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#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
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static struct map_desc bast_iodesc[] __initdata = {
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/* ISA IO areas */
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{
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = PA_CS2(BAST_PA_ISAIO),
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.length = SZ_16M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = PA_CS3(BAST_PA_ISAIO),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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/* bast CPLD control registers, and external interrupt controls */
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{
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.virtual = (u32)BAST_VA_CTRL1,
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.pfn = __phys_to_pfn(BAST_PA_CTRL1),
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.length = SZ_1M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)BAST_VA_CTRL2,
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.pfn = __phys_to_pfn(BAST_PA_CTRL2),
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.length = SZ_1M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)BAST_VA_CTRL3,
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.pfn = __phys_to_pfn(BAST_PA_CTRL3),
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.length = SZ_1M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)BAST_VA_CTRL4,
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.pfn = __phys_to_pfn(BAST_PA_CTRL4),
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.length = SZ_1M,
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.type = MT_DEVICE,
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},
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/* PC104 IRQ mux */
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{
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.virtual = (u32)BAST_VA_PC104_IRQREQ,
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.pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
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.length = SZ_1M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)BAST_VA_PC104_IRQRAW,
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.pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
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.length = SZ_1M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)BAST_VA_PC104_IRQMASK,
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.pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
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.length = SZ_1M,
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.type = MT_DEVICE,
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},
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/* peripheral space... one for each of fast/slow/byte/16bit */
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/* note, ide is only decoded in word space, even though some registers
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* are only 8bit */
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/* slow, byte */
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{ VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
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{ VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
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{ VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
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/* slow, word */
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{ VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
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{ VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
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{ VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
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/* fast, byte */
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{ VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
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{ VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
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{ VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
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/* fast, word */
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{ VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
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{ VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
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{ VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
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};
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#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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/* port 2 is not actually used */
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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}
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};
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/* NAND Flash on BAST board */
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#ifdef CONFIG_PM
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static int bast_pm_suspend(void)
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{
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/* ensure that an nRESET is not generated on resume. */
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gpio_direction_output(S3C2410_GPA(21), 1);
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return 0;
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}
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static void bast_pm_resume(void)
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{
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s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
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}
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#else
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#define bast_pm_suspend NULL
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#define bast_pm_resume NULL
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#endif
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static struct syscore_ops bast_pm_syscore_ops = {
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.suspend = bast_pm_suspend,
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.resume = bast_pm_resume,
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};
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static int smartmedia_map[] = { 0 };
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static int chip0_map[] = { 1 };
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static int chip1_map[] = { 2 };
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static int chip2_map[] = { 3 };
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static struct mtd_partition __initdata bast_default_nand_part[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_16K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_16K,
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.offset = SZ_16K,
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},
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[2] = {
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.name = "user",
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.offset = SZ_4M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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/* the bast has 4 selectable slots for nand-flash, the three
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* on-board chip areas, as well as the external SmartMedia
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* slot.
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*
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* Note, there is no current hot-plug support for the SmartMedia
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* socket.
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*/
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static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
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[0] = {
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.name = "SmartMedia",
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.nr_chips = 1,
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.nr_map = smartmedia_map,
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.options = NAND_SCAN_SILENT_NODEV,
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.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
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.partitions = bast_default_nand_part,
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},
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[1] = {
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.name = "chip0",
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.nr_chips = 1,
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.nr_map = chip0_map,
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.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
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.partitions = bast_default_nand_part,
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},
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[2] = {
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.name = "chip1",
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.nr_chips = 1,
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.nr_map = chip1_map,
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.options = NAND_SCAN_SILENT_NODEV,
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.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
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.partitions = bast_default_nand_part,
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},
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[3] = {
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.name = "chip2",
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.nr_chips = 1,
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.nr_map = chip2_map,
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.options = NAND_SCAN_SILENT_NODEV,
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.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
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.partitions = bast_default_nand_part,
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}
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};
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static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
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{
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unsigned int tmp;
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slot = set->nr_map[slot] & 3;
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pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
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slot, set, set->nr_map);
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tmp = __raw_readb(BAST_VA_CTRL2);
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tmp &= BAST_CPLD_CTLR2_IDERST;
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tmp |= slot;
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tmp |= BAST_CPLD_CTRL2_WNAND;
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pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
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__raw_writeb(tmp, BAST_VA_CTRL2);
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}
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static struct s3c2410_platform_nand __initdata bast_nand_info = {
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.tacls = 30,
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.twrph0 = 60,
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.twrph1 = 60,
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.nr_sets = ARRAY_SIZE(bast_nand_sets),
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.sets = bast_nand_sets,
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.select_chip = bast_nand_select,
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.ecc_mode = NAND_ECC_SOFT,
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};
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/* DM9000 */
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static struct resource bast_dm9k_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
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[1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
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[2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
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| IORESOURCE_IRQ_HIGHLEVEL),
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};
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/* for the moment we limit ourselves to 16bit IO until some
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* better IO routines can be written and tested
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*/
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static struct dm9000_plat_data bast_dm9k_platdata = {
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.flags = DM9000_PLATF_16BITONLY,
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};
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static struct platform_device bast_device_dm9k = {
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.name = "dm9000",
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.id = 0,
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.num_resources = ARRAY_SIZE(bast_dm9k_resource),
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.resource = bast_dm9k_resource,
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.dev = {
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.platform_data = &bast_dm9k_platdata,
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}
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};
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/* serial devices */
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#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
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#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
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#define SERIAL_CLK (1843200)
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static struct plat_serial8250_port bast_sio_data[] = {
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[0] = {
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.mapbase = SERIAL_BASE + 0x2f8,
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.irq = BAST_IRQ_PCSERIAL1,
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.flags = SERIAL_FLAGS,
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.iotype = UPIO_MEM,
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.regshift = 0,
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.uartclk = SERIAL_CLK,
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},
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[1] = {
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.mapbase = SERIAL_BASE + 0x3f8,
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.irq = BAST_IRQ_PCSERIAL2,
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.flags = SERIAL_FLAGS,
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.iotype = UPIO_MEM,
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.regshift = 0,
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.uartclk = SERIAL_CLK,
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},
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{ }
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};
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static struct platform_device bast_sio = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = &bast_sio_data,
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},
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};
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/* we have devices on the bus which cannot work much over the
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* standard 100KHz i2c bus frequency
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*/
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static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
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.flags = 0,
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.slave_addr = 0x10,
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.frequency = 100*1000,
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};
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/* Asix AX88796 10/100 ethernet controller */
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static struct ax_plat_data bast_asix_platdata = {
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.flags = AXFLG_MAC_FROMDEV,
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.wordlength = 2,
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.dcr_val = 0x48,
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.rcr_val = 0x40,
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};
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static struct resource bast_asix_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
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[1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
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[2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
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};
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static struct platform_device bast_device_asix = {
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.name = "ax88796",
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.id = 0,
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.num_resources = ARRAY_SIZE(bast_asix_resource),
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.resource = bast_asix_resource,
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.dev = {
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.platform_data = &bast_asix_platdata
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}
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};
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/* Asix AX88796 10/100 ethernet controller parallel port */
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static struct resource bast_asixpp_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
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0x30 * 0x20),
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};
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static struct platform_device bast_device_axpp = {
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.name = "ax88796-pp",
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.id = 0,
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.num_resources = ARRAY_SIZE(bast_asixpp_resource),
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.resource = bast_asixpp_resource,
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};
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/* LCD/VGA controller */
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static struct s3c2410fb_display __initdata bast_lcd_info[] = {
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.pixclock = 33333,
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.xres = 640,
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.yres = 480,
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.bpp = 4,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon5 = 0x00014b02,
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},
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.pixclock = 33333,
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.xres = 640,
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.yres = 480,
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.bpp = 8,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon5 = 0x00014b02,
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},
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.pixclock = 33333,
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.xres = 640,
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.yres = 480,
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.bpp = 16,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon5 = 0x00014b02,
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},
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};
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/* LCD/VGA controller */
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static struct s3c2410fb_mach_info __initdata bast_fb_info = {
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.displays = bast_lcd_info,
|
|
.num_displays = ARRAY_SIZE(bast_lcd_info),
|
|
.default_display = 1,
|
|
};
|
|
|
|
/* I2C devices fitted. */
|
|
|
|
static struct i2c_board_info bast_i2c_devs[] __initdata = {
|
|
{
|
|
I2C_BOARD_INFO("tlv320aic23", 0x1a),
|
|
}, {
|
|
I2C_BOARD_INFO("simtec-pmu", 0x6b),
|
|
}, {
|
|
I2C_BOARD_INFO("ch7013", 0x75),
|
|
},
|
|
};
|
|
|
|
static struct s3c_hwmon_pdata bast_hwmon_info = {
|
|
/* LCD contrast (0-6.6V) */
|
|
.in[0] = &(struct s3c_hwmon_chcfg) {
|
|
.name = "lcd-contrast",
|
|
.mult = 3300,
|
|
.div = 512,
|
|
},
|
|
/* LED current feedback */
|
|
.in[1] = &(struct s3c_hwmon_chcfg) {
|
|
.name = "led-feedback",
|
|
.mult = 3300,
|
|
.div = 1024,
|
|
},
|
|
/* LCD feedback (0-6.6V) */
|
|
.in[2] = &(struct s3c_hwmon_chcfg) {
|
|
.name = "lcd-feedback",
|
|
.mult = 3300,
|
|
.div = 512,
|
|
},
|
|
/* Vcore (1.8-2.0V), Vref 3.3V */
|
|
.in[3] = &(struct s3c_hwmon_chcfg) {
|
|
.name = "vcore",
|
|
.mult = 3300,
|
|
.div = 1024,
|
|
},
|
|
};
|
|
|
|
/* Standard BAST devices */
|
|
// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
|
|
|
|
static struct platform_device *bast_devices[] __initdata = {
|
|
&s3c2410_device_dclk,
|
|
&s3c_device_ohci,
|
|
&s3c_device_lcd,
|
|
&s3c_device_wdt,
|
|
&s3c_device_i2c0,
|
|
&s3c_device_rtc,
|
|
&s3c_device_nand,
|
|
&s3c_device_adc,
|
|
&s3c_device_hwmon,
|
|
&bast_device_dm9k,
|
|
&bast_device_asix,
|
|
&bast_device_axpp,
|
|
&bast_sio,
|
|
};
|
|
|
|
static struct s3c_cpufreq_board __initdata bast_cpufreq = {
|
|
.refresh = 7800, /* 7.8usec */
|
|
.auto_io = 1,
|
|
.need_io = 1,
|
|
};
|
|
|
|
static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
|
|
.have_mic = 1,
|
|
.have_lout = 1,
|
|
};
|
|
|
|
static void __init bast_map_io(void)
|
|
{
|
|
s3c_hwmon_set_platdata(&bast_hwmon_info);
|
|
|
|
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
|
|
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
|
|
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
|
}
|
|
|
|
static void __init bast_init_time(void)
|
|
{
|
|
s3c2410_init_clocks(12000000);
|
|
samsung_timer_init();
|
|
}
|
|
|
|
static void __init bast_init(void)
|
|
{
|
|
register_syscore_ops(&bast_pm_syscore_ops);
|
|
|
|
s3c_i2c0_set_platdata(&bast_i2c_info);
|
|
s3c_nand_set_platdata(&bast_nand_info);
|
|
s3c24xx_fb_set_platdata(&bast_fb_info);
|
|
platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
|
|
|
|
i2c_register_board_info(0, bast_i2c_devs,
|
|
ARRAY_SIZE(bast_i2c_devs));
|
|
|
|
usb_simtec_init();
|
|
nor_simtec_init();
|
|
simtec_audio_add(NULL, true, &bast_audio);
|
|
|
|
WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
|
|
|
|
s3c_cpufreq_setboard(&bast_cpufreq);
|
|
}
|
|
|
|
MACHINE_START(BAST, "Simtec-BAST")
|
|
/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
|
|
.atag_offset = 0x100,
|
|
.map_io = bast_map_io,
|
|
.init_irq = s3c2410_init_irq,
|
|
.init_machine = bast_init,
|
|
.init_time = bast_init_time,
|
|
MACHINE_END
|