556 lines
12 KiB
C
556 lines
12 KiB
C
/*
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* arch/arm/mach-spear3xx/spear320.c
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*
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* SPEAr320 machine source file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/ptrace.h>
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#include <asm/irq.h>
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#include <plat/shirq.h>
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#include <mach/generic.h>
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#include <mach/hardware.h>
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/* pad multiplexing support */
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/* muxing registers */
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#define PAD_MUX_CONFIG_REG 0x0C
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#define MODE_CONFIG_REG 0x10
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/* modes */
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#define AUTO_NET_SMII_MODE (1 << 0)
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#define AUTO_NET_MII_MODE (1 << 1)
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#define AUTO_EXP_MODE (1 << 2)
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#define SMALL_PRINTERS_MODE (1 << 3)
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#define ALL_MODES 0xF
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struct pmx_mode spear320_auto_net_smii_mode = {
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.id = AUTO_NET_SMII_MODE,
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.name = "Automation Networking SMII Mode",
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.mask = 0x00,
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};
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struct pmx_mode spear320_auto_net_mii_mode = {
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.id = AUTO_NET_MII_MODE,
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.name = "Automation Networking MII Mode",
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.mask = 0x01,
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};
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struct pmx_mode spear320_auto_exp_mode = {
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.id = AUTO_EXP_MODE,
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.name = "Automation Expanded Mode",
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.mask = 0x02,
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};
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struct pmx_mode spear320_small_printers_mode = {
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.id = SMALL_PRINTERS_MODE,
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.name = "Small Printers Mode",
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.mask = 0x03,
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};
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/* devices */
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static struct pmx_dev_mode pmx_clcd_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE,
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.mask = 0x0,
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},
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};
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struct pmx_dev spear320_pmx_clcd = {
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.name = "clcd",
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.modes = pmx_clcd_modes,
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.mode_count = ARRAY_SIZE(pmx_clcd_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_emi_modes[] = {
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{
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.ids = AUTO_EXP_MODE,
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.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
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},
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};
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struct pmx_dev spear320_pmx_emi = {
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.name = "emi",
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.modes = pmx_emi_modes,
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.mode_count = ARRAY_SIZE(pmx_emi_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_fsmc_modes[] = {
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{
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.ids = ALL_MODES,
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.mask = 0x0,
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},
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};
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struct pmx_dev spear320_pmx_fsmc = {
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.name = "fsmc",
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.modes = pmx_fsmc_modes,
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.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_spp_modes[] = {
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{
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.ids = SMALL_PRINTERS_MODE,
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.mask = 0x0,
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},
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};
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struct pmx_dev spear320_pmx_spp = {
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.name = "spp",
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.modes = pmx_spp_modes,
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.mode_count = ARRAY_SIZE(pmx_spp_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_sdhci_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
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SMALL_PRINTERS_MODE,
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.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
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},
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};
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struct pmx_dev spear320_pmx_sdhci = {
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.name = "sdhci",
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.modes = pmx_sdhci_modes,
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.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_i2s_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
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.mask = PMX_UART0_MODEM_MASK,
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},
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};
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struct pmx_dev spear320_pmx_i2s = {
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.name = "i2s",
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.modes = pmx_i2s_modes,
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.mode_count = ARRAY_SIZE(pmx_i2s_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_uart1_modes[] = {
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{
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.ids = ALL_MODES,
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.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
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},
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};
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struct pmx_dev spear320_pmx_uart1 = {
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.name = "uart1",
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.modes = pmx_uart1_modes,
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.mode_count = ARRAY_SIZE(pmx_uart1_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
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{
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.ids = AUTO_EXP_MODE,
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.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
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PMX_SSP_CS_MASK,
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}, {
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.ids = SMALL_PRINTERS_MODE,
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.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
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PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
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},
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};
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struct pmx_dev spear320_pmx_uart1_modem = {
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.name = "uart1_modem",
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.modes = pmx_uart1_modem_modes,
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.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_uart2_modes[] = {
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{
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.ids = ALL_MODES,
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.mask = PMX_FIRDA_MASK,
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},
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};
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struct pmx_dev spear320_pmx_uart2 = {
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.name = "uart2",
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.modes = pmx_uart2_modes,
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.mode_count = ARRAY_SIZE(pmx_uart2_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_touchscreen_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE,
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.mask = PMX_SSP_CS_MASK,
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},
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};
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struct pmx_dev spear320_pmx_touchscreen = {
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.name = "touchscreen",
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.modes = pmx_touchscreen_modes,
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.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_can_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
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.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
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PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
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},
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};
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struct pmx_dev spear320_pmx_can = {
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.name = "can",
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.modes = pmx_can_modes,
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.mode_count = ARRAY_SIZE(pmx_can_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
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.mask = PMX_SSP_CS_MASK,
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},
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};
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struct pmx_dev spear320_pmx_sdhci_led = {
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.name = "sdhci_led",
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.modes = pmx_sdhci_led_modes,
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.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_pwm0_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
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.mask = PMX_UART0_MODEM_MASK,
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}, {
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.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev spear320_pmx_pwm0 = {
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.name = "pwm0",
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.modes = pmx_pwm0_modes,
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.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_pwm1_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
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.mask = PMX_UART0_MODEM_MASK,
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}, {
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.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev spear320_pmx_pwm1 = {
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.name = "pwm1",
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.modes = pmx_pwm1_modes,
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.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_pwm2_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
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.mask = PMX_SSP_CS_MASK,
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}, {
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.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev spear320_pmx_pwm2 = {
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.name = "pwm2",
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.modes = pmx_pwm2_modes,
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.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_pwm3_modes[] = {
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{
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.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev spear320_pmx_pwm3 = {
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.name = "pwm3",
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.modes = pmx_pwm3_modes,
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.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_ssp1_modes[] = {
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{
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.ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev spear320_pmx_ssp1 = {
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.name = "ssp1",
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.modes = pmx_ssp1_modes,
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.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_ssp2_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev spear320_pmx_ssp2 = {
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.name = "ssp2",
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.modes = pmx_ssp2_modes,
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.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_mii1_modes[] = {
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{
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.ids = AUTO_NET_MII_MODE,
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.mask = 0x0,
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},
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};
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struct pmx_dev spear320_pmx_mii1 = {
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.name = "mii1",
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.modes = pmx_mii1_modes,
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.mode_count = ARRAY_SIZE(pmx_mii1_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_smii0_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev spear320_pmx_smii0 = {
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.name = "smii0",
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.modes = pmx_smii0_modes,
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.mode_count = ARRAY_SIZE(pmx_smii0_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_smii1_modes[] = {
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{
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.ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev spear320_pmx_smii1 = {
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.name = "smii1",
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.modes = pmx_smii1_modes,
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.mode_count = ARRAY_SIZE(pmx_smii1_modes),
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.enb_on_reset = 1,
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};
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static struct pmx_dev_mode pmx_i2c1_modes[] = {
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{
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.ids = AUTO_EXP_MODE,
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.mask = 0x0,
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},
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};
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struct pmx_dev spear320_pmx_i2c1 = {
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.name = "i2c1",
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.modes = pmx_i2c1_modes,
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.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
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.enb_on_reset = 1,
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};
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/* pmx driver structure */
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static struct pmx_driver pmx_driver = {
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.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
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.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
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};
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/* spear3xx shared irq */
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static struct shirq_dev_config shirq_ras1_config[] = {
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{
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.virq = SPEAR320_VIRQ_EMI,
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.status_mask = SPEAR320_EMI_IRQ_MASK,
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.clear_mask = SPEAR320_EMI_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_CLCD,
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.status_mask = SPEAR320_CLCD_IRQ_MASK,
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.clear_mask = SPEAR320_CLCD_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_SPP,
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.status_mask = SPEAR320_SPP_IRQ_MASK,
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.clear_mask = SPEAR320_SPP_IRQ_MASK,
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},
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};
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static struct spear_shirq shirq_ras1 = {
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.irq = SPEAR3XX_IRQ_GEN_RAS_1,
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.dev_config = shirq_ras1_config,
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.dev_count = ARRAY_SIZE(shirq_ras1_config),
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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static struct shirq_dev_config shirq_ras3_config[] = {
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{
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.virq = SPEAR320_VIRQ_PLGPIO,
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.enb_mask = SPEAR320_GPIO_IRQ_MASK,
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.status_mask = SPEAR320_GPIO_IRQ_MASK,
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.clear_mask = SPEAR320_GPIO_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_I2S_PLAY,
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.enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
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.status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
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.clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_I2S_REC,
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.enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
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.status_mask = SPEAR320_I2S_REC_IRQ_MASK,
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.clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
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},
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};
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static struct spear_shirq shirq_ras3 = {
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.irq = SPEAR3XX_IRQ_GEN_RAS_3,
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.dev_config = shirq_ras3_config,
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.dev_count = ARRAY_SIZE(shirq_ras3_config),
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.regs = {
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.enb_reg = SPEAR320_INT_ENB_MASK_REG,
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.reset_to_enb = 1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
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{
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.virq = SPEAR320_VIRQ_CANU,
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.status_mask = SPEAR320_CAN_U_IRQ_MASK,
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.clear_mask = SPEAR320_CAN_U_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_CANL,
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.status_mask = SPEAR320_CAN_L_IRQ_MASK,
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.clear_mask = SPEAR320_CAN_L_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_UART1,
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.status_mask = SPEAR320_UART1_IRQ_MASK,
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.clear_mask = SPEAR320_UART1_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_UART2,
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.status_mask = SPEAR320_UART2_IRQ_MASK,
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.clear_mask = SPEAR320_UART2_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_SSP1,
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.status_mask = SPEAR320_SSP1_IRQ_MASK,
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.clear_mask = SPEAR320_SSP1_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_SSP2,
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.status_mask = SPEAR320_SSP2_IRQ_MASK,
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.clear_mask = SPEAR320_SSP2_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_SMII0,
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.status_mask = SPEAR320_SMII0_IRQ_MASK,
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.clear_mask = SPEAR320_SMII0_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_MII1_SMII1,
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.status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
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.clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
|
|
}, {
|
|
.virq = SPEAR320_VIRQ_WAKEUP_SMII0,
|
|
.status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
|
|
.clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
|
|
}, {
|
|
.virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
|
|
.status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
|
|
.clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
|
|
}, {
|
|
.virq = SPEAR320_VIRQ_I2C1,
|
|
.status_mask = SPEAR320_I2C1_IRQ_MASK,
|
|
.clear_mask = SPEAR320_I2C1_IRQ_MASK,
|
|
},
|
|
};
|
|
|
|
static struct spear_shirq shirq_intrcomm_ras = {
|
|
.irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
|
|
.dev_config = shirq_intrcomm_ras_config,
|
|
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
|
|
.regs = {
|
|
.enb_reg = -1,
|
|
.status_reg = SPEAR320_INT_STS_MASK_REG,
|
|
.status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
|
|
.clear_reg = SPEAR320_INT_CLR_MASK_REG,
|
|
.reset_to_clear = 1,
|
|
},
|
|
};
|
|
|
|
/* Add spear320 specific devices here */
|
|
|
|
/* spear320 routines */
|
|
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
|
u8 pmx_dev_count)
|
|
{
|
|
void __iomem *base;
|
|
int ret = 0;
|
|
|
|
/* call spear3xx family common init function */
|
|
spear3xx_init();
|
|
|
|
/* shared irq registration */
|
|
base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
|
|
if (base) {
|
|
/* shirq 1 */
|
|
shirq_ras1.regs.base = base;
|
|
ret = spear_shirq_register(&shirq_ras1);
|
|
if (ret)
|
|
printk(KERN_ERR "Error registering Shared IRQ 1\n");
|
|
|
|
/* shirq 3 */
|
|
shirq_ras3.regs.base = base;
|
|
ret = spear_shirq_register(&shirq_ras3);
|
|
if (ret)
|
|
printk(KERN_ERR "Error registering Shared IRQ 3\n");
|
|
|
|
/* shirq 4 */
|
|
shirq_intrcomm_ras.regs.base = base;
|
|
ret = spear_shirq_register(&shirq_intrcomm_ras);
|
|
if (ret)
|
|
printk(KERN_ERR "Error registering Shared IRQ 4\n");
|
|
}
|
|
|
|
/* pmx initialization */
|
|
pmx_driver.base = base;
|
|
pmx_driver.mode = pmx_mode;
|
|
pmx_driver.devs = pmx_devs;
|
|
pmx_driver.devs_count = pmx_dev_count;
|
|
|
|
ret = pmx_register(&pmx_driver);
|
|
if (ret)
|
|
printk(KERN_ERR "padmux: registration failed. err no: %d\n",
|
|
ret);
|
|
}
|