55 lines
2.2 KiB
Plaintext
55 lines
2.2 KiB
Plaintext
ST Microelectronics Flexible Static Memory Controller (FSMC)
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NAND Interface
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Required properties:
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- compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
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- reg : Address range of the mtd chip
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- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
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Optional properties:
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- bank-width : Width (in bytes) of the device. If not present, the width
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defaults to 1 byte
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- nand-skip-bbtscan: Indicates the BBT scanning should be skipped
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- timings: array of 6 bytes for NAND timings. The meanings of these bytes
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are:
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byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
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are valid. Zero means one clockcycle, 15 means 16 clock
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cycles.
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byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
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byte 2 THIZ : number of HCLK clock cycles during which the data bus is
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kept in Hi-Z (tristate) after the start of a write access.
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Only valid for write transactions. Zero means zero cycles,
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255 means 255 cycles.
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byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
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when writing) after the command deassertation. Zero means
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one cycle, 255 means 256 cycles.
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byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
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NAND flash in response to SMWAITn. Zero means 1 cycle,
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255 means 256 cycles.
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byte 5 TSET : number of HCLK clock cycles to assert the address before the
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command is asserted. Zero means one cycle, 255 means 256
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cycles.
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- bank: default NAND bank to use (0-3 are valid, 0 is the default).
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Example:
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fsmc: flash@d1800000 {
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compatible = "st,spear600-fsmc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd1800000 0x1000 /* FSMC Register */
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0xd2000000 0x0010 /* NAND Base DATA */
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0xd2020000 0x0010 /* NAND Base ADDR */
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0xd2010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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bank-width = <1>;
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nand-skip-bbtscan;
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timings = /bits/ 8 <0 0 0 2 3 0>;
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bank = <1>;
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partition@0 {
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...
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};
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};
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