336 lines
9.9 KiB
C
336 lines
9.9 KiB
C
/*
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* max77693-irq.c - Interrupt controller support for MAX77693
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*
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* Copyright (C) 2012 Samsung Electronics Co.Ltd
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* SangYoung Son <hello.son@samsung.com>
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*
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* This program is not provided / owned by Maxim Integrated Products.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This driver is based on max8997-irq.c
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*/
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/max77693.h>
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#include <linux/mfd/max77693-private.h>
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static const u8 max77693_mask_reg[] = {
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[LED_INT] = MAX77693_LED_REG_FLASH_INT_MASK,
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[TOPSYS_INT] = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
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[CHG_INT] = MAX77693_CHG_REG_CHG_INT_MASK,
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[MUIC_INT1] = MAX77693_MUIC_REG_INTMASK1,
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[MUIC_INT2] = MAX77693_MUIC_REG_INTMASK2,
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[MUIC_INT3] = MAX77693_MUIC_REG_INTMASK3,
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};
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static struct regmap *max77693_get_regmap(struct max77693_dev *max77693,
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enum max77693_irq_source src)
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{
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switch (src) {
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case LED_INT ... CHG_INT:
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return max77693->regmap;
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case MUIC_INT1 ... MUIC_INT3:
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return max77693->regmap_muic;
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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struct max77693_irq_data {
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int mask;
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enum max77693_irq_source group;
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};
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#define DECLARE_IRQ(idx, _group, _mask) \
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[(idx)] = { .group = (_group), .mask = (_mask) }
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static const struct max77693_irq_data max77693_irqs[] = {
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DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0),
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DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1),
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DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2),
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DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3),
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DECLARE_IRQ(MAX77693_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4),
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DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0),
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DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1),
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DECLARE_IRQ(MAX77693_TOPSYS_IRQ_LOWSYS_INT, TOPSYS_INT, 1 << 3),
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DECLARE_IRQ(MAX77693_CHG_IRQ_BYP_I, CHG_INT, 1 << 0),
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DECLARE_IRQ(MAX77693_CHG_IRQ_THM_I, CHG_INT, 1 << 2),
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DECLARE_IRQ(MAX77693_CHG_IRQ_BAT_I, CHG_INT, 1 << 3),
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DECLARE_IRQ(MAX77693_CHG_IRQ_CHG_I, CHG_INT, 1 << 4),
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DECLARE_IRQ(MAX77693_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_LOW, MUIC_INT1, 1 << 1),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_ERR, MUIC_INT1, 1 << 2),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VIDRM, MUIC_INT2, 1 << 5),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_EOC, MUIC_INT3, 1 << 0),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CGMBC, MUIC_INT3, 1 << 1),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_OVP, MUIC_INT3, 1 << 2),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, MUIC_INT3, 1 << 3),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, MUIC_INT3, 1 << 4),
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DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_BAT_DET, MUIC_INT3, 1 << 5),
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};
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static void max77693_irq_lock(struct irq_data *data)
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{
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struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
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mutex_lock(&max77693->irqlock);
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}
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static void max77693_irq_sync_unlock(struct irq_data *data)
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{
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struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
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int i;
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for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
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u8 mask_reg = max77693_mask_reg[i];
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struct regmap *map = max77693_get_regmap(max77693, i);
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if (mask_reg == MAX77693_REG_INVALID ||
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IS_ERR_OR_NULL(map))
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continue;
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max77693->irq_masks_cache[i] = max77693->irq_masks_cur[i];
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max77693_write_reg(map, max77693_mask_reg[i],
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max77693->irq_masks_cur[i]);
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}
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mutex_unlock(&max77693->irqlock);
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}
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static const inline struct max77693_irq_data *
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irq_to_max77693_irq(struct max77693_dev *max77693, int irq)
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{
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return &max77693_irqs[irq];
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}
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static void max77693_irq_mask(struct irq_data *data)
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{
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struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
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const struct max77693_irq_data *irq_data =
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irq_to_max77693_irq(max77693, data->irq);
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if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
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return;
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if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
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max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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else
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max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
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}
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static void max77693_irq_unmask(struct irq_data *data)
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{
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struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
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const struct max77693_irq_data *irq_data =
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irq_to_max77693_irq(max77693, data->irq);
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if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
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return;
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if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
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max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
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else
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max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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}
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static struct irq_chip max77693_irq_chip = {
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.name = "max77693",
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.irq_bus_lock = max77693_irq_lock,
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.irq_bus_sync_unlock = max77693_irq_sync_unlock,
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.irq_mask = max77693_irq_mask,
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.irq_unmask = max77693_irq_unmask,
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};
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#define MAX77693_IRQSRC_CHG (1 << 0)
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#define MAX77693_IRQSRC_TOP (1 << 1)
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#define MAX77693_IRQSRC_FLASH (1 << 2)
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#define MAX77693_IRQSRC_MUIC (1 << 3)
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static irqreturn_t max77693_irq_thread(int irq, void *data)
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{
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struct max77693_dev *max77693 = data;
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u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {};
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u8 irq_src;
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int ret;
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int i, cur_irq;
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ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_INTSRC,
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&irq_src);
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if (ret < 0) {
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dev_err(max77693->dev, "Failed to read interrupt source: %d\n",
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ret);
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return IRQ_NONE;
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}
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if (irq_src & MAX77693_IRQSRC_CHG)
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/* CHG_INT */
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ret = max77693_read_reg(max77693->regmap, MAX77693_CHG_REG_CHG_INT,
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&irq_reg[CHG_INT]);
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if (irq_src & MAX77693_IRQSRC_TOP)
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/* TOPSYS_INT */
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ret = max77693_read_reg(max77693->regmap,
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MAX77693_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]);
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if (irq_src & MAX77693_IRQSRC_FLASH)
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/* LED_INT */
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ret = max77693_read_reg(max77693->regmap,
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MAX77693_LED_REG_FLASH_INT, &irq_reg[LED_INT]);
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if (irq_src & MAX77693_IRQSRC_MUIC)
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/* MUIC INT1 ~ INT3 */
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max77693_bulk_read(max77693->regmap_muic, MAX77693_MUIC_REG_INT1,
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MAX77693_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]);
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/* Apply masking */
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for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
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if (i >= MUIC_INT1 && i <= MUIC_INT3)
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irq_reg[i] &= max77693->irq_masks_cur[i];
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else
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irq_reg[i] &= ~max77693->irq_masks_cur[i];
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}
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/* Report */
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for (i = 0; i < MAX77693_IRQ_NR; i++) {
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if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask) {
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cur_irq = irq_find_mapping(max77693->irq_domain, i);
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if (cur_irq)
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handle_nested_irq(cur_irq);
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}
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}
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return IRQ_HANDLED;
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}
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int max77693_irq_resume(struct max77693_dev *max77693)
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{
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if (max77693->irq)
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max77693_irq_thread(0, max77693);
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return 0;
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}
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static int max77693_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct max77693_dev *max77693 = d->host_data;
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irq_set_chip_data(irq, max77693);
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irq_set_chip_and_handler(irq, &max77693_irq_chip, handle_edge_irq);
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irq_set_nested_thread(irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(irq, IRQF_VALID);
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#else
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irq_set_noprobe(irq);
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#endif
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return 0;
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}
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static struct irq_domain_ops max77693_irq_domain_ops = {
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.map = max77693_irq_domain_map,
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};
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int max77693_irq_init(struct max77693_dev *max77693)
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{
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struct irq_domain *domain;
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int i;
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int ret = 0;
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u8 intsrc_mask;
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mutex_init(&max77693->irqlock);
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/* Mask individual interrupt sources */
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for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
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struct regmap *map;
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/* MUIC IRQ 0:MASK 1:NOT MASK */
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/* Other IRQ 1:MASK 0:NOT MASK */
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if (i >= MUIC_INT1 && i <= MUIC_INT3) {
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max77693->irq_masks_cur[i] = 0x00;
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max77693->irq_masks_cache[i] = 0x00;
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} else {
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max77693->irq_masks_cur[i] = 0xff;
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max77693->irq_masks_cache[i] = 0xff;
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}
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map = max77693_get_regmap(max77693, i);
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if (IS_ERR_OR_NULL(map))
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continue;
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if (max77693_mask_reg[i] == MAX77693_REG_INVALID)
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continue;
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if (i >= MUIC_INT1 && i <= MUIC_INT3)
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max77693_write_reg(map, max77693_mask_reg[i], 0x00);
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else
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max77693_write_reg(map, max77693_mask_reg[i], 0xff);
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}
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domain = irq_domain_add_linear(NULL, MAX77693_IRQ_NR,
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&max77693_irq_domain_ops, max77693);
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if (!domain) {
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dev_err(max77693->dev, "could not create irq domain\n");
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ret = -ENODEV;
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goto err_irq;
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}
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max77693->irq_domain = domain;
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/* Unmask max77693 interrupt */
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ret = max77693_read_reg(max77693->regmap,
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MAX77693_PMIC_REG_INTSRC_MASK, &intsrc_mask);
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if (ret < 0) {
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dev_err(max77693->dev, "fail to read PMIC register\n");
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goto err_irq;
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}
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intsrc_mask &= ~(MAX77693_IRQSRC_CHG);
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intsrc_mask &= ~(MAX77693_IRQSRC_FLASH);
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intsrc_mask &= ~(MAX77693_IRQSRC_MUIC);
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ret = max77693_write_reg(max77693->regmap,
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MAX77693_PMIC_REG_INTSRC_MASK, intsrc_mask);
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if (ret < 0) {
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dev_err(max77693->dev, "fail to write PMIC register\n");
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goto err_irq;
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}
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ret = request_threaded_irq(max77693->irq, NULL, max77693_irq_thread,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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"max77693-irq", max77693);
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if (ret)
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dev_err(max77693->dev, "Failed to request IRQ %d: %d\n",
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max77693->irq, ret);
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err_irq:
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return ret;
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}
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void max77693_irq_exit(struct max77693_dev *max77693)
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{
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if (max77693->irq)
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free_irq(max77693->irq, max77693);
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}
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